mirror of
https://github.com/torvalds/linux.git
synced 2025-11-07 20:19:47 +02:00
15426dbb65
CWSR fails on Raven if the control stack is MTYPE_UC, which is used for regular GART mappings. As a workaround we map it using MTYPE_NC. The MEC firmware expects the control stack at one page offset from the start of the MQD so it is part of the MQD allocation on GFXv9. AMDGPU added a memory allocation flag just for this purpose. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yong Zhao <yong.zhao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
||
|---|---|---|
| .. | ||
| asic_reg | ||
| ivsrcid | ||
| linux | ||
| amd_acpi.h | ||
| amd_pcie.h | ||
| amd_pcie_helpers.h | ||
| amd_shared.h | ||
| atom-bits.h | ||
| atom-names.h | ||
| atom-types.h | ||
| atombios.h | ||
| atomfirmware.h | ||
| atomfirmwareid.h | ||
| cgs_common.h | ||
| cik_structs.h | ||
| displayobject.h | ||
| dm_pp_interface.h | ||
| kgd_kfd_interface.h | ||
| kgd_pp_interface.h | ||
| pptable.h | ||
| soc15_hw_ip.h | ||
| soc15_ih_clientid.h | ||
| v9_structs.h | ||
| vega10_enum.h | ||
| vega10_ip_offset.h | ||
| vega20_ip_offset.h | ||
| vi_structs.h | ||