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47d80a68f1
Thanks to Christoph Hellwig for pointing out a cleaner way to do this, as my approach was quite ugly. CC: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
75 lines
2.6 KiB
C
75 lines
2.6 KiB
C
/*
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2014 Darius Rad <darius@bluespec.com>
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* Copyright (C) 2017 SiFive
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/syscalls.h>
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#include <asm/unistd.h>
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#include <asm/cacheflush.h>
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static long riscv_sys_mmap(unsigned long addr, unsigned long len,
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unsigned long prot, unsigned long flags,
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unsigned long fd, off_t offset,
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unsigned long page_shift_offset)
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{
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if (unlikely(offset & (~PAGE_MASK >> page_shift_offset)))
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return -EINVAL;
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return ksys_mmap_pgoff(addr, len, prot, flags, fd,
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offset >> (PAGE_SHIFT - page_shift_offset));
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}
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#ifdef CONFIG_64BIT
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SYSCALL_DEFINE6(mmap, unsigned long, addr, unsigned long, len,
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unsigned long, prot, unsigned long, flags,
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unsigned long, fd, off_t, offset)
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{
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return riscv_sys_mmap(addr, len, prot, flags, fd, offset, 0);
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}
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#else
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SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len,
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unsigned long, prot, unsigned long, flags,
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unsigned long, fd, off_t, offset)
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{
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/*
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* Note that the shift for mmap2 is constant (12),
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* regardless of PAGE_SIZE
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*/
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return riscv_sys_mmap(addr, len, prot, flags, fd, offset, 12);
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}
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#endif /* !CONFIG_64BIT */
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/*
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* Allows the instruction cache to be flushed from userspace. Despite RISC-V
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* having a direct 'fence.i' instruction available to userspace (which we
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* can't trap!), that's not actually viable when running on Linux because the
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* kernel might schedule a process on another hart. There is no way for
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* userspace to handle this without invoking the kernel (as it doesn't know the
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* thread->hart mappings), so we've defined a RISC-V specific system call to
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* flush the instruction cache.
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*
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* sys_riscv_flush_icache() is defined to flush the instruction cache over an
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* address range, with the flush applying to either all threads or just the
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* caller. We don't currently do anything with the address range, that's just
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* in there for forwards compatibility.
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*/
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SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, uintptr_t, end,
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uintptr_t, flags)
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{
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/* Check the reserved flags. */
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if (unlikely(flags & ~SYS_RISCV_FLUSH_ICACHE_ALL))
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return -EINVAL;
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flush_icache_mm(current->mm, flags & SYS_RISCV_FLUSH_ICACHE_LOCAL);
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return 0;
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}
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