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	Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
		
			
				
	
	
		
			137 lines
		
	
	
	
		
			3.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			137 lines
		
	
	
	
		
			3.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * IBM ASM Service Processor Device Driver
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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 *
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 * Copyright (C) IBM Corporation, 2004
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 *
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 * Author: Max Asböck <amax@us.ibm.com>
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 *
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 */
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/* Condor service processor specific hardware definitions */
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#ifndef __IBMASM_CONDOR_H__
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#define __IBMASM_CONDOR_H__
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#include <asm/io.h>
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#define VENDORID_IBM	0x1014
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#define DEVICEID_RSA	0x010F
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#define GET_MFA_ADDR(x)  (x & 0xFFFFFF00)
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#define MAILBOX_FULL(x)  (x & 0x00000001)
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#define NO_MFAS_AVAILABLE     0xFFFFFFFF
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#define INBOUND_QUEUE_PORT   0x40  /* contains address of next free MFA */
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#define OUTBOUND_QUEUE_PORT  0x44  /* contains address of posted MFA    */
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#define SP_INTR_MASK	0x00000008
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#define UART_INTR_MASK	0x00000010
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#define INTR_STATUS_REGISTER   0x13A0
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#define INTR_CONTROL_REGISTER  0x13A4
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#define SCOUT_COM_A_BASE         0x0000
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#define SCOUT_COM_B_BASE         0x0100
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#define SCOUT_COM_C_BASE         0x0200
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#define SCOUT_COM_D_BASE         0x0300
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static inline int sp_interrupt_pending(void __iomem *base_address)
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{
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	return SP_INTR_MASK & readl(base_address + INTR_STATUS_REGISTER);
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}
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static inline int uart_interrupt_pending(void __iomem *base_address)
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{
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	return UART_INTR_MASK & readl(base_address + INTR_STATUS_REGISTER);
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}
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static inline void ibmasm_enable_interrupts(void __iomem *base_address, int mask)
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{
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	void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER;
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	writel( readl(ctrl_reg) & ~mask, ctrl_reg);
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}
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static inline void ibmasm_disable_interrupts(void __iomem *base_address, int mask)
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{
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	void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER;
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	writel( readl(ctrl_reg) | mask, ctrl_reg);
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}
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static inline void enable_sp_interrupts(void __iomem *base_address)
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{
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	ibmasm_enable_interrupts(base_address, SP_INTR_MASK);
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}
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static inline void disable_sp_interrupts(void __iomem *base_address)
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{
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	ibmasm_disable_interrupts(base_address, SP_INTR_MASK);
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}
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static inline void enable_uart_interrupts(void __iomem *base_address)
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{
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	ibmasm_enable_interrupts(base_address, UART_INTR_MASK);
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}
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static inline void disable_uart_interrupts(void __iomem *base_address)
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{
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	ibmasm_disable_interrupts(base_address, UART_INTR_MASK);
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}
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#define valid_mfa(mfa)	( (mfa) != NO_MFAS_AVAILABLE )
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static inline u32 get_mfa_outbound(void __iomem *base_address)
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{
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	int retry;
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	u32 mfa;
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	for (retry=0; retry<=10; retry++) {
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		mfa = readl(base_address + OUTBOUND_QUEUE_PORT);
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		if (valid_mfa(mfa))
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			break;
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	}
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	return mfa;
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}
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static inline void set_mfa_outbound(void __iomem *base_address, u32 mfa)
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{
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	writel(mfa, base_address + OUTBOUND_QUEUE_PORT);
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}
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static inline u32 get_mfa_inbound(void __iomem *base_address)
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{
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	u32 mfa = readl(base_address + INBOUND_QUEUE_PORT);
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	if (MAILBOX_FULL(mfa))
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		return 0;
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	return mfa;
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}
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static inline void set_mfa_inbound(void __iomem *base_address, u32 mfa)
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{
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	writel(mfa, base_address + INBOUND_QUEUE_PORT);
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}
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static inline struct i2o_message *get_i2o_message(void __iomem *base_address, u32 mfa)
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{
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	return (struct i2o_message *)(GET_MFA_ADDR(mfa) + base_address);
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}
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#endif /* __IBMASM_CONDOR_H__ */
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