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4d80b7c507
The phy_id property is deprecated and phy-handle has to be used instead. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
542 lines
13 KiB
Text
542 lines
13 KiB
Text
/*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "dra74x.dtsi"
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#include "dra7-evm-common.dtsi"
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#include "dra74x-mmc-iodelay.dtsi"
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/ {
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model = "TI DRA742";
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compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
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};
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evm_12v0: fixedregulator-evm_12v0 {
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/* main supply */
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compatible = "regulator-fixed";
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regulator-name = "evm_12v0";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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regulator-always-on;
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regulator-boot-on;
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};
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evm_1v8_sw: fixedregulator-evm_1v8 {
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compatible = "regulator-fixed";
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regulator-name = "evm_1v8";
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vin-supply = <&smps9_reg>;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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evm_3v3_sd: fixedregulator-sd {
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compatible = "regulator-fixed";
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regulator-name = "evm_3v3_sd";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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enable-active-high;
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gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
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};
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evm_3v3_sw: fixedregulator-evm_3v3_sw {
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compatible = "regulator-fixed";
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regulator-name = "evm_3v3_sw";
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vin-supply = <&sysen1>;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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aic_dvdd: fixedregulator-aic_dvdd {
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/* TPS77018DBVT */
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compatible = "regulator-fixed";
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regulator-name = "aic_dvdd";
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vin-supply = <&evm_3v3_sw>;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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evm_3v3: fixedregulator-evm3v3 {
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/* Output of Cntlr A of TPS43351-Q1 on dra7-evm */
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compatible = "regulator-fixed";
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regulator-name = "evm_3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&evm_12v0>;
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regulator-always-on;
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regulator-boot-on;
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};
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evm_5v0: fixedregulator-evm_5v0 {
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/* Output of Cntlr B of TPS43351-Q1 on dra7-evm */
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compatible = "regulator-fixed";
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regulator-name = "evm_5v0";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&evm_12v0>;
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regulator-always-on;
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regulator-boot-on;
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};
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evm_3v6: fixedregulator-evm_3v6 {
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compatible = "regulator-fixed";
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regulator-name = "evm_3v6";
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regulator-min-microvolt = <3600000>;
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regulator-max-microvolt = <3600000>;
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vin-supply = <&evm_5v0>;
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regulator-always-on;
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regulator-boot-on;
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};
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vmmcwl_fixed: fixedregulator-mmcwl {
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compatible = "regulator-fixed";
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regulator-name = "vmmcwl_fixed";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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gpio = <&gpio5 8 0>;
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startup-delay-us = <70000>;
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enable-active-high;
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};
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vtt_fixed: fixedregulator-vtt {
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compatible = "regulator-fixed";
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regulator-name = "vtt_fixed";
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regulator-min-microvolt = <1350000>;
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regulator-max-microvolt = <1350000>;
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regulator-always-on;
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regulator-boot-on;
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enable-active-high;
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vin-supply = <&sysen2>;
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gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
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};
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};
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&dra7_pmx_core {
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dcan1_pins_default: dcan1_pins_default {
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pinctrl-single,pins = <
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DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
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DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
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>;
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};
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dcan1_pins_sleep: dcan1_pins_sleep {
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pinctrl-single,pins = <
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DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
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DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
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>;
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};
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <400000>;
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tps659038: tps659038@58 {
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compatible = "ti,tps659038";
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reg = <0x58>;
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ti,palmas-override-powerhold;
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ti,system-power-controller;
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tps659038_pmic {
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compatible = "ti,tps659038-pmic";
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regulators {
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smps123_reg: smps123 {
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/* VDD_MPU */
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regulator-name = "smps123";
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regulator-min-microvolt = < 850000>;
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regulator-max-microvolt = <1250000>;
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regulator-always-on;
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regulator-boot-on;
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};
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smps45_reg: smps45 {
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/* VDD_DSPEVE */
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regulator-name = "smps45";
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regulator-min-microvolt = < 850000>;
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regulator-max-microvolt = <1250000>;
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regulator-always-on;
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regulator-boot-on;
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};
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smps6_reg: smps6 {
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/* VDD_GPU - over VDD_SMPS6 */
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regulator-name = "smps6";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1250000>;
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regulator-always-on;
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regulator-boot-on;
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};
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smps7_reg: smps7 {
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/* CORE_VDD */
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regulator-name = "smps7";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1150000>;
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regulator-always-on;
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regulator-boot-on;
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};
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smps8_reg: smps8 {
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/* VDD_IVAHD */
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regulator-name = "smps8";
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regulator-min-microvolt = < 850000>;
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regulator-max-microvolt = <1250000>;
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regulator-always-on;
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regulator-boot-on;
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};
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smps9_reg: smps9 {
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/* VDDS1V8 */
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regulator-name = "smps9";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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ldo1_reg: ldo1 {
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/* LDO1_OUT --> SDIO */
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regulator-name = "ldo1";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-boot-on;
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};
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ldo2_reg: ldo2 {
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/* VDD_RTCIO */
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/* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
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regulator-name = "ldo2";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-boot-on;
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};
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ldo3_reg: ldo3 {
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/* VDDA_1V8_PHY */
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regulator-name = "ldo3";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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ldo9_reg: ldo9 {
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/* VDD_RTC */
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regulator-name = "ldo9";
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regulator-min-microvolt = <1050000>;
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regulator-max-microvolt = <1050000>;
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regulator-always-on;
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regulator-boot-on;
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regulator-allow-bypass;
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};
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ldoln_reg: ldoln {
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/* VDDA_1V8_PLL */
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regulator-name = "ldoln";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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ldousb_reg: ldousb {
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/* VDDA_3V_USB: VDDA_USBHS33 */
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regulator-name = "ldousb";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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/* REGEN1 is unused */
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regen2: regen2 {
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/* Needed for PMIC internal resources */
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regulator-name = "regen2";
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regulator-boot-on;
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regulator-always-on;
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};
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/* REGEN3 is unused */
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sysen1: sysen1 {
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/* PMIC_REGEN_3V3 */
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regulator-name = "sysen1";
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regulator-boot-on;
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regulator-always-on;
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};
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sysen2: sysen2 {
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/* PMIC_REGEN_DDR */
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regulator-name = "sysen2";
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regulator-boot-on;
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regulator-always-on;
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};
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};
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};
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};
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pcf_lcd: gpio@20 {
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compatible = "ti,pcf8575", "nxp,pcf8575";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&gpio6>;
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interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pcf_gpio_21: gpio@21 {
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compatible = "ti,pcf8575", "nxp,pcf8575";
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reg = <0x21>;
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lines-initial-states = <0x1408>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&gpio6>;
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interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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tlv320aic3106: tlv320aic3106@19 {
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#sound-dai-cells = <0>;
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compatible = "ti,tlv320aic3106";
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reg = <0x19>;
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adc-settle-ms = <40>;
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ai3x-micbias-vg = <1>; /* 2.0V */
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status = "okay";
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/* Regulators */
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AVDD-supply = <&evm_3v3_sw>;
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IOVDD-supply = <&evm_3v3_sw>;
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DRVDD-supply = <&evm_3v3_sw>;
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DVDD-supply = <&aic_dvdd>;
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};
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};
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&i2c2 {
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status = "okay";
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clock-frequency = <400000>;
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pcf_hdmi: gpio@26 {
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compatible = "ti,pcf8575", "nxp,pcf8575";
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reg = <0x26>;
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gpio-controller;
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#gpio-cells = <2>;
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p1 {
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/* vin6_sel_s0: high: VIN6, low: audio */
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gpio-hog;
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gpios = <1 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "vin6_sel_s0";
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};
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};
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};
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&mmc1 {
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status = "okay";
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vmmc-supply = <&evm_3v3_sd>;
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vqmmc-supply = <&ldo1_reg>;
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bus-width = <4>;
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/*
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* SDCD signal is not being used here - using the fact that GPIO mode
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* is always hardwired.
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*/
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cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104";
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pinctrl-0 = <&mmc1_pins_default>;
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pinctrl-1 = <&mmc1_pins_hs>;
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pinctrl-2 = <&mmc1_pins_sdr12>;
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pinctrl-3 = <&mmc1_pins_sdr25>;
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pinctrl-4 = <&mmc1_pins_sdr50>;
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pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>;
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pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;
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pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
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pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
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};
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&mmc2 {
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status = "okay";
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vmmc-supply = <&evm_1v8_sw>;
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vqmmc-supply = <&evm_1v8_sw>;
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bus-width = <8>;
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non-removable;
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pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v";
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pinctrl-0 = <&mmc2_pins_default>;
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pinctrl-1 = <&mmc2_pins_hs>;
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pinctrl-2 = <&mmc2_pins_ddr_1_8v_rev11 &mmc2_iodelay_ddr_1_8v_rev11_conf>;
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pinctrl-3 = <&mmc2_pins_ddr_rev20>;
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pinctrl-4 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev11_conf>;
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pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
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};
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&mmc4 {
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status = "okay";
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vmmc-supply = <&evm_3v6>;
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vqmmc-supply = <&vmmcwl_fixed>;
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pinctrl-names = "default-rev11", "default", "hs-rev11", "hs", "sdr12-rev11", "sdr12", "sdr25-rev11", "sdr25";
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pinctrl-0 = <&mmc4_pins_default &mmc4_iodelay_ds_rev11_conf>;
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pinctrl-1 = <&mmc4_pins_default &mmc4_iodelay_ds_rev20_conf>;
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pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
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pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
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pinctrl-4 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
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pinctrl-5 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
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pinctrl-6 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
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pinctrl-7 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
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};
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&cpu0 {
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vdd-supply = <&smps123_reg>;
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};
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&elm {
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status = "okay";
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};
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&gpmc {
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/*
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* For the existing IOdelay configuration via U-Boot we don't
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* support NAND on dra7-evm. Keep it disabled. Enabling it
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* requires a different configuration by U-Boot.
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*/
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status = "disabled";
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ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
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nand@0,0 {
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* device IO registers */
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
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ti,nand-xfer-type = "prefetch-dma";
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ti,nand-ecc-opt = "bch8";
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ti,elm-id = <&elm>;
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nand-bus-width = <16>;
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gpmc,device-width = <2>;
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <80>;
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gpmc,cs-wr-off-ns = <80>;
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gpmc,adv-on-ns = <0>;
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gpmc,adv-rd-off-ns = <60>;
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gpmc,adv-wr-off-ns = <60>;
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gpmc,we-on-ns = <10>;
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gpmc,we-off-ns = <50>;
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gpmc,oe-on-ns = <4>;
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gpmc,oe-off-ns = <40>;
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gpmc,access-ns = <40>;
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gpmc,wr-access-ns = <80>;
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gpmc,rd-cycle-ns = <80>;
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gpmc,wr-cycle-ns = <80>;
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wr-data-mux-bus-ns = <0>;
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/* MTD partition table */
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/* All SPL-* partitions are sized to minimal length
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* which can be independently programmable. For
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* NAND flash this is equal to size of erase-block */
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "NAND.SPL";
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reg = <0x00000000 0x000020000>;
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};
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partition@1 {
|
|
label = "NAND.SPL.backup1";
|
|
reg = <0x00020000 0x00020000>;
|
|
};
|
|
partition@2 {
|
|
label = "NAND.SPL.backup2";
|
|
reg = <0x00040000 0x00020000>;
|
|
};
|
|
partition@3 {
|
|
label = "NAND.SPL.backup3";
|
|
reg = <0x00060000 0x00020000>;
|
|
};
|
|
partition@4 {
|
|
label = "NAND.u-boot-spl-os";
|
|
reg = <0x00080000 0x00040000>;
|
|
};
|
|
partition@5 {
|
|
label = "NAND.u-boot";
|
|
reg = <0x000c0000 0x00100000>;
|
|
};
|
|
partition@6 {
|
|
label = "NAND.u-boot-env";
|
|
reg = <0x001c0000 0x00020000>;
|
|
};
|
|
partition@7 {
|
|
label = "NAND.u-boot-env.backup1";
|
|
reg = <0x001e0000 0x00020000>;
|
|
};
|
|
partition@8 {
|
|
label = "NAND.kernel";
|
|
reg = <0x00200000 0x00800000>;
|
|
};
|
|
partition@9 {
|
|
label = "NAND.file-system";
|
|
reg = <0x00a00000 0x0f600000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&usb2_phy1 {
|
|
phy-supply = <&ldousb_reg>;
|
|
};
|
|
|
|
&usb2_phy2 {
|
|
phy-supply = <&ldousb_reg>;
|
|
};
|
|
|
|
&gpio7 {
|
|
ti,no-reset-on-init;
|
|
ti,no-idle-on-init;
|
|
};
|
|
|
|
&mac {
|
|
status = "okay";
|
|
dual_emac;
|
|
};
|
|
|
|
&cpsw_emac0 {
|
|
phy-handle = <ðphy0>;
|
|
phy-mode = "rgmii";
|
|
dual_emac_res_vlan = <1>;
|
|
};
|
|
|
|
&cpsw_emac1 {
|
|
phy-handle = <ðphy1>;
|
|
phy-mode = "rgmii";
|
|
dual_emac_res_vlan = <2>;
|
|
};
|
|
|
|
&davinci_mdio {
|
|
ethphy0: ethernet-phy@2 {
|
|
reg = <2>;
|
|
};
|
|
|
|
ethphy1: ethernet-phy@3 {
|
|
reg = <3>;
|
|
};
|
|
};
|
|
|
|
&dcan1 {
|
|
status = "ok";
|
|
pinctrl-names = "default", "sleep", "active";
|
|
pinctrl-0 = <&dcan1_pins_sleep>;
|
|
pinctrl-1 = <&dcan1_pins_sleep>;
|
|
pinctrl-2 = <&dcan1_pins_default>;
|
|
};
|