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linux/arch/m68k/include/asm/m528xsim.h
Greg Kroah-Hartman b24413180f License cleanup: add SPDX GPL-2.0 license identifier to files with no license 
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.

By default all files without license information are under the default
license of the kernel, which is GPL version 2.

Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier.  The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.

This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.

How this work was done:

Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
 - file had no licensing information it it.
 - file was a */uapi/* one with no licensing information in it,
 - file was a */uapi/* one with existing licensing information,

Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.

The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne.  Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.

The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed.  Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.

Criteria used to select files for SPDX license identifier tagging was:
 - Files considered eligible had to be source code files.
 - Make and config files were included as candidates if they contained >5
   lines of source
 - File already had some variant of a license header in it (even if <5
   lines).

All documentation files were explicitly excluded.

The following heuristics were used to determine which SPDX license
identifiers to apply.

 - when both scanners couldn't find any license traces, file was
   considered to have no license information in it, and the top level
   COPYING file license applied.

   For non */uapi/* files that summary was:

   SPDX license identifier                            # files
   ---------------------------------------------------|-------
   GPL-2.0                                              11139

   and resulted in the first patch in this series.

   If that file was a */uapi/* path one, it was "GPL-2.0 WITH
   Linux-syscall-note" otherwise it was "GPL-2.0".  Results of that was:

   SPDX license identifier                            # files
   ---------------------------------------------------|-------
   GPL-2.0 WITH Linux-syscall-note                        930

   and resulted in the second patch in this series.

 - if a file had some form of licensing information in it, and was one
   of the */uapi/* ones, it was denoted with the Linux-syscall-note if
   any GPL family license was found in the file or had no licensing in
   it (per prior point).  Results summary:

   SPDX license identifier                            # files
   ---------------------------------------------------|------
   GPL-2.0 WITH Linux-syscall-note                       270
   GPL-2.0+ WITH Linux-syscall-note                      169
   ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause)    21
   ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)    17
   LGPL-2.1+ WITH Linux-syscall-note                      15
   GPL-1.0+ WITH Linux-syscall-note                       14
   ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause)    5
   LGPL-2.0+ WITH Linux-syscall-note                       4
   LGPL-2.1 WITH Linux-syscall-note                        3
   ((GPL-2.0 WITH Linux-syscall-note) OR MIT)              3
   ((GPL-2.0 WITH Linux-syscall-note) AND MIT)             1

   and that resulted in the third patch in this series.

 - when the two scanners agreed on the detected license(s), that became
   the concluded license(s).

 - when there was disagreement between the two scanners (one detected a
   license but the other didn't, or they both detected different
   licenses) a manual inspection of the file occurred.

 - In most cases a manual inspection of the information in the file
   resulted in a clear resolution of the license that should apply (and
   which scanner probably needed to revisit its heuristics).

 - When it was not immediately clear, the license identifier was
   confirmed with lawyers working with the Linux Foundation.

 - If there was any question as to the appropriate license identifier,
   the file was flagged for further research and to be revisited later
   in time.

In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.

Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights.  The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.

Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.

In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.

Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
 - a full scancode scan run, collecting the matched texts, detected
   license ids and scores
 - reviewing anything where there was a license detected (about 500+
   files) to ensure that the applied SPDX license was correct
 - reviewing anything where there was no detection but the patch license
   was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
   SPDX license was correct

This produced a worksheet with 20 files needing minor correction.  This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.

These .csv files were then reviewed by Greg.  Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected.  This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.)  Finally Greg ran the script using the .csv files to
generate the patches.

Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-02 11:10:55 +01:00

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/* SPDX-License-Identifier: GPL-2.0 */
/****************************************************************************/
/*
* m528xsim.h -- ColdFire 5280/5282 System Integration Module support.
*
* (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com)
*/
/****************************************************************************/
#ifndef m528xsim_h
#define m528xsim_h
/****************************************************************************/
#define CPU_NAME "COLDFIRE(m528x)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK MCF_CLK
#include <asm/m52xxacr.h>
/*
* Define the 5280/5282 SIM register set addresses.
*/
#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
#define MCFINTC_IRLR 0x18 /* */
#define MCFINTC_IACKL 0x19 /* */
#define MCFINTC_ICR0 0x40 /* Base ICR register */
#define MCFINT_VECBASE 64 /* Vector base number */
#define MCFINT_UART0 13 /* Interrupt number for UART0 */
#define MCFINT_UART1 14 /* Interrupt number for UART1 */
#define MCFINT_UART2 15 /* Interrupt number for UART2 */
#define MCFINT_I2C0 17 /* Interrupt number for I2C */
#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
#define MCFINT_FECRX0 23 /* Interrupt number for FEC */
#define MCFINT_FECTX0 27 /* Interrupt number for FEC */
#define MCFINT_FECENTC0 29 /* Interrupt number for FEC */
#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
#define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0)
/*
* SDRAM configuration registers.
*/
#define MCFSIM_DCR (MCF_IPSBAR + 0x00000044) /* Control */
#define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */
#define MCFSIM_DMR0 (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */
#define MCFSIM_DACR1 (MCF_IPSBAR + 0x00000050) /* Base address 1 */
#define MCFSIM_DMR1 (MCF_IPSBAR + 0x00000054) /* Address mask 1 */
/*
* DMA unit base addresses.
*/
#define MCFDMA_BASE0 (MCF_IPSBAR + 0x00000100)
#define MCFDMA_BASE1 (MCF_IPSBAR + 0x00000140)
#define MCFDMA_BASE2 (MCF_IPSBAR + 0x00000180)
#define MCFDMA_BASE3 (MCF_IPSBAR + 0x000001C0)
/*
* UART module.
*/
#define MCFUART_BASE0 (MCF_IPSBAR + 0x00000200)
#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000240)
#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000280)
/*
* FEC ethernet module.
*/
#define MCFFEC_BASE0 (MCF_IPSBAR + 0x00001000)
#define MCFFEC_SIZE0 0x800
/*
* QSPI module.
*/
#define MCFQSPI_BASE (MCF_IPSBAR + 0x340)
#define MCFQSPI_SIZE 0x40
#define MCFQSPI_CS0 147
#define MCFQSPI_CS1 148
#define MCFQSPI_CS2 149
#define MCFQSPI_CS3 150
/*
* GPIO registers
*/
#define MCFGPIO_PODR_A (MCF_IPSBAR + 0x00100000)
#define MCFGPIO_PODR_B (MCF_IPSBAR + 0x00100001)
#define MCFGPIO_PODR_C (MCF_IPSBAR + 0x00100002)
#define MCFGPIO_PODR_D (MCF_IPSBAR + 0x00100003)
#define MCFGPIO_PODR_E (MCF_IPSBAR + 0x00100004)
#define MCFGPIO_PODR_F (MCF_IPSBAR + 0x00100005)
#define MCFGPIO_PODR_G (MCF_IPSBAR + 0x00100006)
#define MCFGPIO_PODR_H (MCF_IPSBAR + 0x00100007)
#define MCFGPIO_PODR_J (MCF_IPSBAR + 0x00100008)
#define MCFGPIO_PODR_DD (MCF_IPSBAR + 0x00100009)
#define MCFGPIO_PODR_EH (MCF_IPSBAR + 0x0010000A)
#define MCFGPIO_PODR_EL (MCF_IPSBAR + 0x0010000B)
#define MCFGPIO_PODR_AS (MCF_IPSBAR + 0x0010000C)
#define MCFGPIO_PODR_QS (MCF_IPSBAR + 0x0010000D)
#define MCFGPIO_PODR_SD (MCF_IPSBAR + 0x0010000E)
#define MCFGPIO_PODR_TC (MCF_IPSBAR + 0x0010000F)
#define MCFGPIO_PODR_TD (MCF_IPSBAR + 0x00100010)
#define MCFGPIO_PODR_UA (MCF_IPSBAR + 0x00100011)
#define MCFGPIO_PDDR_A (MCF_IPSBAR + 0x00100014)
#define MCFGPIO_PDDR_B (MCF_IPSBAR + 0x00100015)
#define MCFGPIO_PDDR_C (MCF_IPSBAR + 0x00100016)
#define MCFGPIO_PDDR_D (MCF_IPSBAR + 0x00100017)
#define MCFGPIO_PDDR_E (MCF_IPSBAR + 0x00100018)
#define MCFGPIO_PDDR_F (MCF_IPSBAR + 0x00100019)
#define MCFGPIO_PDDR_G (MCF_IPSBAR + 0x0010001A)
#define MCFGPIO_PDDR_H (MCF_IPSBAR + 0x0010001B)
#define MCFGPIO_PDDR_J (MCF_IPSBAR + 0x0010001C)
#define MCFGPIO_PDDR_DD (MCF_IPSBAR + 0x0010001D)
#define MCFGPIO_PDDR_EH (MCF_IPSBAR + 0x0010001E)
#define MCFGPIO_PDDR_EL (MCF_IPSBAR + 0x0010001F)
#define MCFGPIO_PDDR_AS (MCF_IPSBAR + 0x00100020)
#define MCFGPIO_PDDR_QS (MCF_IPSBAR + 0x00100021)
#define MCFGPIO_PDDR_SD (MCF_IPSBAR + 0x00100022)
#define MCFGPIO_PDDR_TC (MCF_IPSBAR + 0x00100023)
#define MCFGPIO_PDDR_TD (MCF_IPSBAR + 0x00100024)
#define MCFGPIO_PDDR_UA (MCF_IPSBAR + 0x00100025)
#define MCFGPIO_PPDSDR_A (MCF_IPSBAR + 0x00100028)
#define MCFGPIO_PPDSDR_B (MCF_IPSBAR + 0x00100029)
#define MCFGPIO_PPDSDR_C (MCF_IPSBAR + 0x0010002A)
#define MCFGPIO_PPDSDR_D (MCF_IPSBAR + 0x0010002B)
#define MCFGPIO_PPDSDR_E (MCF_IPSBAR + 0x0010002C)
#define MCFGPIO_PPDSDR_F (MCF_IPSBAR + 0x0010002D)
#define MCFGPIO_PPDSDR_G (MCF_IPSBAR + 0x0010002E)
#define MCFGPIO_PPDSDR_H (MCF_IPSBAR + 0x0010002F)
#define MCFGPIO_PPDSDR_J (MCF_IPSBAR + 0x00100030)
#define MCFGPIO_PPDSDR_DD (MCF_IPSBAR + 0x00100031)
#define MCFGPIO_PPDSDR_EH (MCF_IPSBAR + 0x00100032)
#define MCFGPIO_PPDSDR_EL (MCF_IPSBAR + 0x00100033)
#define MCFGPIO_PPDSDR_AS (MCF_IPSBAR + 0x00100034)
#define MCFGPIO_PPDSDR_QS (MCF_IPSBAR + 0x00100035)
#define MCFGPIO_PPDSDR_SD (MCF_IPSBAR + 0x00100036)
#define MCFGPIO_PPDSDR_TC (MCF_IPSBAR + 0x00100037)
#define MCFGPIO_PPDSDR_TD (MCF_IPSBAR + 0x00100038)
#define MCFGPIO_PPDSDR_UA (MCF_IPSBAR + 0x00100039)
#define MCFGPIO_PCLRR_A (MCF_IPSBAR + 0x0010003C)
#define MCFGPIO_PCLRR_B (MCF_IPSBAR + 0x0010003D)
#define MCFGPIO_PCLRR_C (MCF_IPSBAR + 0x0010003E)
#define MCFGPIO_PCLRR_D (MCF_IPSBAR + 0x0010003F)
#define MCFGPIO_PCLRR_E (MCF_IPSBAR + 0x00100040)
#define MCFGPIO_PCLRR_F (MCF_IPSBAR + 0x00100041)
#define MCFGPIO_PCLRR_G (MCF_IPSBAR + 0x00100042)
#define MCFGPIO_PCLRR_H (MCF_IPSBAR + 0x00100043)
#define MCFGPIO_PCLRR_J (MCF_IPSBAR + 0x00100044)
#define MCFGPIO_PCLRR_DD (MCF_IPSBAR + 0x00100045)
#define MCFGPIO_PCLRR_EH (MCF_IPSBAR + 0x00100046)
#define MCFGPIO_PCLRR_EL (MCF_IPSBAR + 0x00100047)
#define MCFGPIO_PCLRR_AS (MCF_IPSBAR + 0x00100048)
#define MCFGPIO_PCLRR_QS (MCF_IPSBAR + 0x00100049)
#define MCFGPIO_PCLRR_SD (MCF_IPSBAR + 0x0010004A)
#define MCFGPIO_PCLRR_TC (MCF_IPSBAR + 0x0010004B)
#define MCFGPIO_PCLRR_TD (MCF_IPSBAR + 0x0010004C)
#define MCFGPIO_PCLRR_UA (MCF_IPSBAR + 0x0010004D)
#define MCFGPIO_PBCDPAR (MCF_IPSBAR + 0x00100050)
#define MCFGPIO_PFPAR (MCF_IPSBAR + 0x00100051)
#define MCFGPIO_PEPAR (MCF_IPSBAR + 0x00100052)
#define MCFGPIO_PJPAR (MCF_IPSBAR + 0x00100054)
#define MCFGPIO_PSDPAR (MCF_IPSBAR + 0x00100055)
#define MCFGPIO_PASPAR (MCF_IPSBAR + 0x00100056)
#define MCFGPIO_PEHLPAR (MCF_IPSBAR + 0x00100058)
#define MCFGPIO_PQSPAR (MCF_IPSBAR + 0x00100059)
#define MCFGPIO_PTCPAR (MCF_IPSBAR + 0x0010005A)
#define MCFGPIO_PTDPAR (MCF_IPSBAR + 0x0010005B)
#define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C)
/*
* PIT timer base addresses.
*/
#define MCFPIT_BASE1 (MCF_IPSBAR + 0x00150000)
#define MCFPIT_BASE2 (MCF_IPSBAR + 0x00160000)
#define MCFPIT_BASE3 (MCF_IPSBAR + 0x00170000)
#define MCFPIT_BASE4 (MCF_IPSBAR + 0x00180000)
/*
* Edge Port registers
*/
#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x00130000)
#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x00130002)
#define MCFEPORT_EPIER (MCF_IPSBAR + 0x00130003)
#define MCFEPORT_EPDR (MCF_IPSBAR + 0x00130004)
#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x00130005)
#define MCFEPORT_EPFR (MCF_IPSBAR + 0x00130006)
/*
* Queued ADC registers
*/
#define MCFQADC_PORTQA (MCF_IPSBAR + 0x00190006)
#define MCFQADC_PORTQB (MCF_IPSBAR + 0x00190007)
#define MCFQADC_DDRQA (MCF_IPSBAR + 0x00190008)
#define MCFQADC_DDRQB (MCF_IPSBAR + 0x00190009)
/*
* General Purpose Timers registers
*/
#define MCFGPTA_GPTPORT (MCF_IPSBAR + 0x001A001D)
#define MCFGPTA_GPTDDR (MCF_IPSBAR + 0x001A001E)
#define MCFGPTB_GPTPORT (MCF_IPSBAR + 0x001B001D)
#define MCFGPTB_GPTDDR (MCF_IPSBAR + 0x001B001E)
/*
*
* definitions for generic gpio support
*
*/
#define MCFGPIO_PODR MCFGPIO_PODR_A /* port output data */
#define MCFGPIO_PDDR MCFGPIO_PDDR_A /* port data direction */
#define MCFGPIO_PPDR MCFGPIO_PPDSDR_A/* port pin data */
#define MCFGPIO_SETR MCFGPIO_PPDSDR_A/* set output */
#define MCFGPIO_CLRR MCFGPIO_PCLRR_A /* clr output */
#define MCFGPIO_IRQ_MAX 8
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
#define MCFGPIO_PIN_MAX 180
/*
* Reset Control Unit (relative to IPSBAR).
*/
#define MCF_RCR (MCF_IPSBAR + 0x110000)
#define MCF_RSR (MCF_IPSBAR + 0x110001)
#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
/*
* I2C module
*/
#define MCFI2C_BASE0 (MCF_IPSBAR + 0x300)
#define MCFI2C_SIZE0 0x40
/****************************************************************************/
#endif /* m528xsim_h */
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