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7034228792
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
114 lines
2.3 KiB
C
114 lines
2.3 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000 Harald Koerfgen
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*/
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#ifndef __ASM_IP32_INTS_H
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#define __ASM_IP32_INTS_H
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#include <asm/irq.h>
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/*
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* This list reflects the assignment of interrupt numbers to
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* interrupting events. Order is fairly irrelevant to handling
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* priority. This differs from irix.
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*/
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enum ip32_irq_no {
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/*
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* CPU interrupts are 0 ... 7
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*/
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CRIME_IRQ_BASE = MIPS_CPU_IRQ_BASE + 8,
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/*
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* MACE
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*/
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MACE_VID_IN1_IRQ = CRIME_IRQ_BASE,
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MACE_VID_IN2_IRQ,
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MACE_VID_OUT_IRQ,
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MACE_ETHERNET_IRQ,
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/* SUPERIO, MISC, and AUDIO are MACEISA */
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__MACE_SUPERIO,
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__MACE_MISC,
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__MACE_AUDIO,
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MACE_PCI_BRIDGE_IRQ,
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/*
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* MACEPCI
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*/
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MACEPCI_SCSI0_IRQ,
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MACEPCI_SCSI1_IRQ,
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MACEPCI_SLOT0_IRQ,
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MACEPCI_SLOT1_IRQ,
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MACEPCI_SLOT2_IRQ,
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MACEPCI_SHARED0_IRQ,
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MACEPCI_SHARED1_IRQ,
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MACEPCI_SHARED2_IRQ,
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/*
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* CRIME
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*/
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CRIME_GBE0_IRQ,
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CRIME_GBE1_IRQ,
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CRIME_GBE2_IRQ,
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CRIME_GBE3_IRQ,
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CRIME_CPUERR_IRQ,
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CRIME_MEMERR_IRQ,
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CRIME_RE_EMPTY_E_IRQ,
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CRIME_RE_FULL_E_IRQ,
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CRIME_RE_IDLE_E_IRQ,
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CRIME_RE_EMPTY_L_IRQ,
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CRIME_RE_FULL_L_IRQ,
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CRIME_RE_IDLE_L_IRQ,
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CRIME_SOFT0_IRQ,
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CRIME_SOFT1_IRQ,
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CRIME_SOFT2_IRQ,
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CRIME_SYSCORERR_IRQ = CRIME_SOFT2_IRQ,
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CRIME_VICE_IRQ,
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/*
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* MACEISA
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*/
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MACEISA_AUDIO_SW_IRQ,
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MACEISA_AUDIO_SC_IRQ,
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MACEISA_AUDIO1_DMAT_IRQ,
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MACEISA_AUDIO1_OF_IRQ,
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MACEISA_AUDIO2_DMAT_IRQ,
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MACEISA_AUDIO2_MERR_IRQ,
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MACEISA_AUDIO3_DMAT_IRQ,
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MACEISA_AUDIO3_MERR_IRQ,
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MACEISA_RTC_IRQ,
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MACEISA_KEYB_IRQ,
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/* MACEISA_KEYB_POLL is not an IRQ */
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__MACEISA_KEYB_POLL,
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MACEISA_MOUSE_IRQ,
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/* MACEISA_MOUSE_POLL is not an IRQ */
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__MACEISA_MOUSE_POLL,
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MACEISA_TIMER0_IRQ,
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MACEISA_TIMER1_IRQ,
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MACEISA_TIMER2_IRQ,
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MACEISA_PARALLEL_IRQ,
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MACEISA_PAR_CTXA_IRQ,
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MACEISA_PAR_CTXB_IRQ,
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MACEISA_PAR_MERR_IRQ,
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MACEISA_SERIAL1_IRQ,
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MACEISA_SERIAL1_TDMAT_IRQ,
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MACEISA_SERIAL1_TDMAPR_IRQ,
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MACEISA_SERIAL1_TDMAME_IRQ,
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MACEISA_SERIAL1_RDMAT_IRQ,
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MACEISA_SERIAL1_RDMAOR_IRQ,
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MACEISA_SERIAL2_IRQ,
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MACEISA_SERIAL2_TDMAT_IRQ,
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MACEISA_SERIAL2_TDMAPR_IRQ,
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MACEISA_SERIAL2_TDMAME_IRQ,
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MACEISA_SERIAL2_RDMAT_IRQ,
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MACEISA_SERIAL2_RDMAOR_IRQ,
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IP32_IRQ_MAX = MACEISA_SERIAL2_RDMAOR_IRQ
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};
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#endif /* __ASM_IP32_INTS_H */
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