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65ae8d2621
Hardcode the absence of the MIPS16e2 ASE for all the systems that do so for the MIPS16 ASE already, providing for code to be optimized away. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16097/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
51 lines
1.4 KiB
C
51 lines
1.4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2005 Ilya A. Volynets-Evenbakh
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* Copyright (C) 2005, 07 Ralf Baechle (ralf@linux-mips.org)
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*/
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#ifndef __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H
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#define __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H
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/*
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* R5000 has an interesting "restriction": ll(d)/sc(d)
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* instructions to XKPHYS region simply do uncached bus
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* requests. This breaks all the atomic bitops functions.
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* so, for 64bit IP32 kernel we just don't use ll/sc.
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* This does not affect luserland.
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*/
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#if (defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_NEVADA)) && defined(CONFIG_64BIT)
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#define cpu_has_llsc 0
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#else
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#define cpu_has_llsc 1
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#endif
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/* Settings which are common for all ip32 CPUs */
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#define cpu_has_tlb 1
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#define cpu_has_4kex 1
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#define cpu_has_32fpr 1
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#define cpu_has_counter 1
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#define cpu_has_mips16 0
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#define cpu_has_mips16e2 0
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#define cpu_has_vce 0
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#define cpu_has_cache_cdex_s 0
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#define cpu_has_mcheck 0
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#define cpu_has_ejtag 0
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#define cpu_has_vtag_icache 0
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#define cpu_has_ic_fills_f_dc 0
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#define cpu_has_dsp 0
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#define cpu_has_dsp2 0
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#define cpu_has_4k_cache 1
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#define cpu_has_mipsmt 0
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#define cpu_has_userlocal 0
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#define cpu_has_mips32r1 0
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#define cpu_has_mips32r2 0
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#define cpu_has_mips64r1 0
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#define cpu_has_mips64r2 0
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#endif /* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */
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