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	Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
		
			
				
	
	
		
			208 lines
		
	
	
	
		
			6.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			208 lines
		
	
	
	
		
			6.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _PPC_BOOT_DCR_H_
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#define _PPC_BOOT_DCR_H_
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#define mfdcr(rn) \
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	({	\
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		unsigned long rval; \
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		asm volatile("mfdcr %0,%1" : "=r"(rval) : "i"(rn)); \
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		rval; \
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	})
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#define mtdcr(rn, val) \
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	asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
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#define mfdcrx(rn) \
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	({	\
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		unsigned long rval; \
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		asm volatile("mfdcrx %0,%1" : "=r"(rval) : "r"(rn)); \
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		rval; \
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	})
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#define mtdcrx(rn, val) \
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	({	\
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		asm volatile("mtdcrx %0,%1" : : "r"(rn), "r" (val)); \
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	})
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/* 440GP/440GX SDRAM controller DCRs */
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#define DCRN_SDRAM0_CFGADDR				0x010
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#define DCRN_SDRAM0_CFGDATA				0x011
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#define SDRAM0_READ(offset) ({\
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	mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
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	mfdcr(DCRN_SDRAM0_CFGDATA); })
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#define SDRAM0_WRITE(offset, data) ({\
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	mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
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	mtdcr(DCRN_SDRAM0_CFGDATA, data); })
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#define 	SDRAM0_B0CR				0x40
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#define 	SDRAM0_B1CR				0x44
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#define 	SDRAM0_B2CR				0x48
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#define 	SDRAM0_B3CR				0x4c
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static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR,
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					    SDRAM0_B2CR, SDRAM0_B3CR };
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#define			SDRAM_CONFIG_BANK_ENABLE        0x00000001
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#define			SDRAM_CONFIG_SIZE_MASK          0x000e0000
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#define			SDRAM_CONFIG_BANK_SIZE(reg)	\
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	(0x00400000 << ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17))
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/* 440GP External Bus Controller (EBC) */
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#define DCRN_EBC0_CFGADDR				0x012
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#define DCRN_EBC0_CFGDATA				0x013
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#define   EBC_NUM_BANKS					  8
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#define   EBC_B0CR					  0x00
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#define   EBC_B1CR					  0x01
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#define   EBC_B2CR					  0x02
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#define   EBC_B3CR					  0x03
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#define   EBC_B4CR					  0x04
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#define   EBC_B5CR					  0x05
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#define   EBC_B6CR					  0x06
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#define   EBC_B7CR					  0x07
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#define   EBC_BXCR(n)					  (n)
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#define	    EBC_BXCR_BAS				    0xfff00000
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#define	    EBC_BXCR_BS				  	    0x000e0000
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#define	    EBC_BXCR_BANK_SIZE(reg) \
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	(0x100000 << (((reg) & EBC_BXCR_BS) >> 17))
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#define	    EBC_BXCR_BU				  	    0x00018000
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#define	      EBC_BXCR_BU_OFF			  	      0x00000000
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#define	      EBC_BXCR_BU_RO			  	      0x00008000
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#define	      EBC_BXCR_BU_WO			  	      0x00010000
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#define	      EBC_BXCR_BU_RW			  	      0x00018000
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#define	    EBC_BXCR_BW				  	    0x00006000
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#define   EBC_B0AP					  0x10
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#define   EBC_B1AP					  0x11
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#define   EBC_B2AP					  0x12
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#define   EBC_B3AP					  0x13
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#define   EBC_B4AP					  0x14
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#define   EBC_B5AP					  0x15
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#define   EBC_B6AP					  0x16
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#define   EBC_B7AP					  0x17
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#define   EBC_BXAP(n)					  (0x10+(n))
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#define   EBC_BEAR					  0x20
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#define   EBC_BESR					  0x21
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#define   EBC_CFG					  0x23
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#define   EBC_CID					  0x24
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/* 440GP Clock, PM, chip control */
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#define DCRN_CPC0_SR					0x0b0
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#define DCRN_CPC0_ER					0x0b1
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#define DCRN_CPC0_FR					0x0b2
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#define DCRN_CPC0_SYS0					0x0e0
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#define	  CPC0_SYS0_TUNE				  0xffc00000
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#define	  CPC0_SYS0_FBDV_MASK				  0x003c0000
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#define	  CPC0_SYS0_FWDVA_MASK				  0x00038000
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#define	  CPC0_SYS0_FWDVB_MASK				  0x00007000
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#define	  CPC0_SYS0_OPDV_MASK				  0x00000c00
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#define	  CPC0_SYS0_EPDV_MASK				  0x00000300
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/* Helper macros to compute the actual clock divider values from the
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 * encodings in the CPC0 register */
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#define	  CPC0_SYS0_FBDV(reg) \
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		((((((reg) & CPC0_SYS0_FBDV_MASK) >> 18) - 1) & 0xf) + 1)
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#define	  CPC0_SYS0_FWDVA(reg) \
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		(8 - (((reg) & CPC0_SYS0_FWDVA_MASK) >> 15))
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#define	  CPC0_SYS0_FWDVB(reg) \
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		(8 - (((reg) & CPC0_SYS0_FWDVB_MASK) >> 12))
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#define	  CPC0_SYS0_OPDV(reg) \
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		((((reg) & CPC0_SYS0_OPDV_MASK) >> 10) + 1)
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#define	  CPC0_SYS0_EPDV(reg) \
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		((((reg) & CPC0_SYS0_EPDV_MASK) >> 8) + 1)
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#define	  CPC0_SYS0_EXTSL				  0x00000080
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#define	  CPC0_SYS0_RW_MASK				  0x00000060
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#define	  CPC0_SYS0_RL					  0x00000010
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#define	  CPC0_SYS0_ZMIISL_MASK				  0x0000000c
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#define	  CPC0_SYS0_BYPASS				  0x00000002
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#define	  CPC0_SYS0_NTO1				  0x00000001
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#define DCRN_CPC0_SYS1					0x0e1
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#define DCRN_CPC0_CUST0					0x0e2
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#define DCRN_CPC0_CUST1					0x0e3
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#define DCRN_CPC0_STRP0					0x0e4
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#define DCRN_CPC0_STRP1					0x0e5
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#define DCRN_CPC0_STRP2					0x0e6
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#define DCRN_CPC0_STRP3					0x0e7
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#define DCRN_CPC0_GPIO					0x0e8
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#define DCRN_CPC0_PLB					0x0e9
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#define DCRN_CPC0_CR1					0x0ea
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#define DCRN_CPC0_CR0					0x0eb
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#define	  CPC0_CR0_SWE					  0x80000000
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#define	  CPC0_CR0_CETE					  0x40000000
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#define	  CPC0_CR0_U1FCS				  0x20000000
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#define	  CPC0_CR0_U0DTE				  0x10000000
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#define	  CPC0_CR0_U0DRE				  0x08000000
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#define	  CPC0_CR0_U0DC					  0x04000000
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#define	  CPC0_CR0_U1DTE				  0x02000000
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#define	  CPC0_CR0_U1DRE				  0x01000000
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#define	  CPC0_CR0_U1DC					  0x00800000
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#define	  CPC0_CR0_U0EC					  0x00400000
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#define	  CPC0_CR0_U1EC					  0x00200000
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#define	  CPC0_CR0_UDIV_MASK				  0x001f0000
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#define	  CPC0_CR0_UDIV(reg) \
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		((((reg) & CPC0_CR0_UDIV_MASK) >> 16) + 1)
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#define DCRN_CPC0_MIRQ0					0x0ec
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#define DCRN_CPC0_MIRQ1					0x0ed
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#define DCRN_CPC0_JTAGID				0x0ef
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#define DCRN_MAL0_CFG					0x180
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#define MAL_RESET 0x80000000
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/* 440EP Clock/Power-on Reset regs */
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#define DCRN_CPR0_ADDR	0xc
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#define DCRN_CPR0_DATA	0xd
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#define CPR0_PLLD0	0x60
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#define CPR0_OPBD0	0xc0
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#define CPR0_PERD0	0xe0
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#define CPR0_PRIMBD0	0xa0
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#define CPR0_SCPID	0x120
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#define CPR0_PLLC0	0x40
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/* 405GP Clocking/Power Management/Chip Control regs */
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#define DCRN_CPC0_PLLMR 0xb0
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#define DCRN_405_CPC0_CR0 0xb1
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#define DCRN_405_CPC0_CR1 0xb2
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#define DCRN_405_CPC0_PSR 0xb4
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/* 405EP Clocking/Power Management/Chip Control regs */
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#define DCRN_CPC0_PLLMR0  0xf0
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#define DCRN_CPC0_PLLMR1  0xf4
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#define DCRN_CPC0_UCR     0xf5
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/* 440GX/405EX Clock Control reg */
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#define DCRN_CPR0_CLKUPD				0x020
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#define DCRN_CPR0_PLLC					0x040
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#define DCRN_CPR0_PLLD					0x060
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#define DCRN_CPR0_PRIMAD				0x080
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#define DCRN_CPR0_PRIMBD				0x0a0
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#define DCRN_CPR0_OPBD					0x0c0
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#define DCRN_CPR0_PERD					0x0e0
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#define DCRN_CPR0_MALD					0x100
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#define DCRN_SDR0_CONFIG_ADDR 	0xe
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#define DCRN_SDR0_CONFIG_DATA	0xf
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/* SDR read/write helper macros */
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#define SDR0_READ(offset) ({\
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	mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
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	mfdcr(DCRN_SDR0_CONFIG_DATA); })
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#define SDR0_WRITE(offset, data) ({\
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	mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
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	mtdcr(DCRN_SDR0_CONFIG_DATA, data); })
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#define DCRN_SDR0_UART0		0x0120
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#define DCRN_SDR0_UART1		0x0121
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#define DCRN_SDR0_UART2		0x0122
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#define DCRN_SDR0_UART3		0x0123
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/* CPRs read/write helper macros - based off include/asm-ppc/ibm44x.h */
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#define DCRN_CPR0_CFGADDR				0xc
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#define DCRN_CPR0_CFGDATA				0xd
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#define CPR0_READ(offset) ({\
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	mtdcr(DCRN_CPR0_CFGADDR, offset); \
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	mfdcr(DCRN_CPR0_CFGDATA); })
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#define CPR0_WRITE(offset, data) ({\
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	mtdcr(DCRN_CPR0_CFGADDR, offset); \
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	mtdcr(DCRN_CPR0_CFGDATA, data); })
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#endif	/* _PPC_BOOT_DCR_H_ */
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