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This patch corrects the SPDX License Identifier style in header files related to Clock Drivers for Davinci Socs. For C header files Documentation/process/license-rules.rst mandates C-like comments (opposed to C source files where C++ style should be used) Changes made by using a script provided by Joe Perches here: https://lkml.org/lkml/2019/2/7/46 Suggested-by: Joe Perches <joe@perches.com> Signed-off-by: Nishad Kamdar <nishadkamdar@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
140 lines
4.5 KiB
C
140 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Clock driver for TI Davinci PSC controllers
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*
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* Copyright (C) 2018 David Lechner <david@lechnology.com>
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*/
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#ifndef __CLK_DAVINCI_PLL_H___
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#define __CLK_DAVINCI_PLL_H___
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#include <linux/bitops.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <linux/types.h>
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#define PLL_HAS_CLKMODE BIT(0) /* PLL has PLLCTL[CLKMODE] */
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#define PLL_HAS_PREDIV BIT(1) /* has prediv before PLL */
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#define PLL_PREDIV_ALWAYS_ENABLED BIT(2) /* don't clear DEN bit */
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#define PLL_PREDIV_FIXED_DIV BIT(3) /* fixed divider value */
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#define PLL_HAS_POSTDIV BIT(4) /* has postdiv after PLL */
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#define PLL_POSTDIV_ALWAYS_ENABLED BIT(5) /* don't clear DEN bit */
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#define PLL_POSTDIV_FIXED_DIV BIT(6) /* fixed divider value */
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#define PLL_HAS_EXTCLKSRC BIT(7) /* has selectable bypass */
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#define PLL_PLLM_2X BIT(8) /* PLLM value is 2x (DM365) */
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#define PLL_PREDIV_FIXED8 BIT(9) /* DM355 quirk */
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/** davinci_pll_clk_info - controller-specific PLL info
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* @name: The name of the PLL
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* @unlock_reg: Option CFGCHIP register for unlocking PLL
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* @unlock_mask: Bitmask used with @unlock_reg
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* @pllm_mask: Bitmask for PLLM[PLLM] value
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* @pllm_min: Minimum allowable value for PLLM[PLLM]
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* @pllm_max: Maximum allowable value for PLLM[PLLM]
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* @pllout_min_rate: Minimum allowable rate for PLLOUT
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* @pllout_max_rate: Maximum allowable rate for PLLOUT
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* @flags: Bitmap of PLL_* flags.
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*/
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struct davinci_pll_clk_info {
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const char *name;
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u32 unlock_reg;
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u32 unlock_mask;
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u32 pllm_mask;
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u32 pllm_min;
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u32 pllm_max;
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unsigned long pllout_min_rate;
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unsigned long pllout_max_rate;
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u32 flags;
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};
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#define SYSCLK_ARM_RATE BIT(0) /* Controls ARM rate */
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#define SYSCLK_ALWAYS_ENABLED BIT(1) /* Or bad things happen */
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#define SYSCLK_FIXED_DIV BIT(2) /* Fixed divider */
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/** davinci_pll_sysclk_info - SYSCLKn-specific info
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* @name: The name of the clock
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* @parent_name: The name of the parent clock
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* @id: "n" in "SYSCLKn"
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* @ratio_width: Width (in bits) of RATIO in PLLDIVn register
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* @flags: Bitmap of SYSCLK_* flags.
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*/
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struct davinci_pll_sysclk_info {
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const char *name;
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const char *parent_name;
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u32 id;
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u32 ratio_width;
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u32 flags;
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};
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#define SYSCLK(i, n, p, w, f) \
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static const struct davinci_pll_sysclk_info n = { \
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.name = #n, \
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.parent_name = #p, \
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.id = (i), \
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.ratio_width = (w), \
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.flags = (f), \
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}
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/** davinci_pll_obsclk_info - OBSCLK-specific info
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* @name: The name of the clock
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* @parent_names: Array of names of the parent clocks
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* @num_parents: Length of @parent_names
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* @table: Array of values to write to OCSEL[OCSRC] cooresponding to
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* @parent_names
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* @ocsrc_mask: Bitmask for OCSEL[OCSRC]
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*/
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struct davinci_pll_obsclk_info {
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const char *name;
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const char * const *parent_names;
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u8 num_parents;
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u32 *table;
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u32 ocsrc_mask;
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};
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struct clk *davinci_pll_clk_register(struct device *dev,
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const struct davinci_pll_clk_info *info,
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const char *parent_name,
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void __iomem *base,
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struct regmap *cfgchip);
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struct clk *davinci_pll_auxclk_register(struct device *dev,
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const char *name,
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void __iomem *base);
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struct clk *davinci_pll_sysclkbp_clk_register(struct device *dev,
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const char *name,
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void __iomem *base);
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struct clk *
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davinci_pll_obsclk_register(struct device *dev,
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const struct davinci_pll_obsclk_info *info,
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void __iomem *base);
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struct clk *
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davinci_pll_sysclk_register(struct device *dev,
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const struct davinci_pll_sysclk_info *info,
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void __iomem *base);
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int of_davinci_pll_init(struct device *dev, struct device_node *node,
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const struct davinci_pll_clk_info *info,
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const struct davinci_pll_obsclk_info *obsclk_info,
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const struct davinci_pll_sysclk_info **div_info,
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u8 max_sysclk_id,
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void __iomem *base,
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struct regmap *cfgchip);
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/* Platform-specific callbacks */
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#ifdef CONFIG_ARCH_DAVINCI_DA850
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int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
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void of_da850_pll0_init(struct device_node *node);
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int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
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#endif
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#ifdef CONFIG_ARCH_DAVINCI_DM355
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int dm355_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
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#endif
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#ifdef CONFIG_ARCH_DAVINCI_DM644x
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int dm644x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
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#endif
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#ifdef CONFIG_ARCH_DAVINCI_DM646x
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int dm646x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
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#endif
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#endif /* __CLK_DAVINCI_PLL_H___ */
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