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b3f2f10693
HFPLLs are the main frequency source for Krait CPU clocks. Add support for changing the rate of these PLLs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Craig Tatlor <ctatlor97@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
44 lines
742 B
C
44 lines
742 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __QCOM_CLK_HFPLL_H__
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#define __QCOM_CLK_HFPLL_H__
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#include <linux/clk-provider.h>
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#include <linux/spinlock.h>
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#include "clk-regmap.h"
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struct hfpll_data {
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u32 mode_reg;
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u32 l_reg;
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u32 m_reg;
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u32 n_reg;
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u32 user_reg;
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u32 droop_reg;
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u32 config_reg;
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u32 status_reg;
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u8 lock_bit;
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u32 droop_val;
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u32 config_val;
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u32 user_val;
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u32 user_vco_mask;
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unsigned long low_vco_max_rate;
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unsigned long min_rate;
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unsigned long max_rate;
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};
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struct clk_hfpll {
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struct hfpll_data const *d;
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int init_done;
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struct clk_regmap clkr;
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spinlock_t lock;
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};
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#define to_clk_hfpll(_hw) \
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container_of(to_clk_regmap(_hw), struct clk_hfpll, clkr)
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extern const struct clk_ops clk_ops_hfpll;
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#endif
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