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The pasemi smbus controller uses PCI_FUNC(dev->devfn) to define which number bus to attach to, however this fails when something else is probed first, for example an ATI Radeon graphics card will claim 9 or 10 busses, including the ones the pasemi wants. Patch the driver to call i2c_add_adapter rather than i2c_add_numbered_adapter. Signed-off-by: Darren Stevens <darren@stevens-zone.net> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
417 lines
10 KiB
C
417 lines
10 KiB
C
/*
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* Copyright (C) 2006-2007 PA Semi, Inc
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*
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* SMBus host driver for PA Semi PWRficient
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/stddef.h>
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#include <linux/sched.h>
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#include <linux/i2c.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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static struct pci_driver pasemi_smb_driver;
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struct pasemi_smbus {
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struct pci_dev *dev;
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struct i2c_adapter adapter;
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unsigned long base;
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int size;
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};
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/* Register offsets */
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#define REG_MTXFIFO 0x00
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#define REG_MRXFIFO 0x04
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#define REG_SMSTA 0x14
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#define REG_CTL 0x1c
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/* Register defs */
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#define MTXFIFO_READ 0x00000400
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#define MTXFIFO_STOP 0x00000200
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#define MTXFIFO_START 0x00000100
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#define MTXFIFO_DATA_M 0x000000ff
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#define MRXFIFO_EMPTY 0x00000100
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#define MRXFIFO_DATA_M 0x000000ff
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#define SMSTA_XEN 0x08000000
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#define SMSTA_MTN 0x00200000
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#define CTL_MRR 0x00000400
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#define CTL_MTR 0x00000200
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#define CTL_CLK_M 0x000000ff
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#define CLK_100K_DIV 84
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#define CLK_400K_DIV 21
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static inline void reg_write(struct pasemi_smbus *smbus, int reg, int val)
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{
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dev_dbg(&smbus->dev->dev, "smbus write reg %lx val %08x\n",
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smbus->base + reg, val);
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outl(val, smbus->base + reg);
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}
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static inline int reg_read(struct pasemi_smbus *smbus, int reg)
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{
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int ret;
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ret = inl(smbus->base + reg);
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dev_dbg(&smbus->dev->dev, "smbus read reg %lx val %08x\n",
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smbus->base + reg, ret);
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return ret;
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}
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#define TXFIFO_WR(smbus, reg) reg_write((smbus), REG_MTXFIFO, (reg))
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#define RXFIFO_RD(smbus) reg_read((smbus), REG_MRXFIFO)
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static void pasemi_smb_clear(struct pasemi_smbus *smbus)
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{
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unsigned int status;
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status = reg_read(smbus, REG_SMSTA);
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reg_write(smbus, REG_SMSTA, status);
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}
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static int pasemi_smb_waitready(struct pasemi_smbus *smbus)
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{
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int timeout = 10;
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unsigned int status;
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status = reg_read(smbus, REG_SMSTA);
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while (!(status & SMSTA_XEN) && timeout--) {
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msleep(1);
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status = reg_read(smbus, REG_SMSTA);
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}
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/* Got NACK? */
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if (status & SMSTA_MTN)
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return -ENXIO;
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if (timeout < 0) {
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dev_warn(&smbus->dev->dev, "Timeout, status 0x%08x\n", status);
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reg_write(smbus, REG_SMSTA, status);
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return -ETIME;
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}
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/* Clear XEN */
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reg_write(smbus, REG_SMSTA, SMSTA_XEN);
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return 0;
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}
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static int pasemi_i2c_xfer_msg(struct i2c_adapter *adapter,
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struct i2c_msg *msg, int stop)
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{
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struct pasemi_smbus *smbus = adapter->algo_data;
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int read, i, err;
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u32 rd;
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read = msg->flags & I2C_M_RD ? 1 : 0;
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TXFIFO_WR(smbus, MTXFIFO_START | i2c_8bit_addr_from_msg(msg));
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if (read) {
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TXFIFO_WR(smbus, msg->len | MTXFIFO_READ |
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(stop ? MTXFIFO_STOP : 0));
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err = pasemi_smb_waitready(smbus);
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if (err)
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goto reset_out;
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for (i = 0; i < msg->len; i++) {
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rd = RXFIFO_RD(smbus);
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if (rd & MRXFIFO_EMPTY) {
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err = -ENODATA;
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goto reset_out;
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}
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msg->buf[i] = rd & MRXFIFO_DATA_M;
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}
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} else {
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for (i = 0; i < msg->len - 1; i++)
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TXFIFO_WR(smbus, msg->buf[i]);
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TXFIFO_WR(smbus, msg->buf[msg->len-1] |
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(stop ? MTXFIFO_STOP : 0));
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}
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return 0;
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reset_out:
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reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR |
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(CLK_100K_DIV & CTL_CLK_M)));
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return err;
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}
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static int pasemi_i2c_xfer(struct i2c_adapter *adapter,
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struct i2c_msg *msgs, int num)
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{
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struct pasemi_smbus *smbus = adapter->algo_data;
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int ret, i;
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pasemi_smb_clear(smbus);
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ret = 0;
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for (i = 0; i < num && !ret; i++)
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ret = pasemi_i2c_xfer_msg(adapter, &msgs[i], (i == (num - 1)));
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return ret ? ret : num;
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}
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static int pasemi_smb_xfer(struct i2c_adapter *adapter,
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u16 addr, unsigned short flags, char read_write, u8 command,
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int size, union i2c_smbus_data *data)
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{
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struct pasemi_smbus *smbus = adapter->algo_data;
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unsigned int rd;
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int read_flag, err;
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int len = 0, i;
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/* All our ops take 8-bit shifted addresses */
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addr <<= 1;
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read_flag = read_write == I2C_SMBUS_READ;
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pasemi_smb_clear(smbus);
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switch (size) {
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case I2C_SMBUS_QUICK:
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TXFIFO_WR(smbus, addr | read_flag | MTXFIFO_START |
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MTXFIFO_STOP);
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break;
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case I2C_SMBUS_BYTE:
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TXFIFO_WR(smbus, addr | read_flag | MTXFIFO_START);
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if (read_write)
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TXFIFO_WR(smbus, 1 | MTXFIFO_STOP | MTXFIFO_READ);
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else
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TXFIFO_WR(smbus, MTXFIFO_STOP | command);
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break;
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case I2C_SMBUS_BYTE_DATA:
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TXFIFO_WR(smbus, addr | MTXFIFO_START);
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TXFIFO_WR(smbus, command);
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if (read_write) {
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TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
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TXFIFO_WR(smbus, 1 | MTXFIFO_READ | MTXFIFO_STOP);
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} else {
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TXFIFO_WR(smbus, MTXFIFO_STOP | data->byte);
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}
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break;
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case I2C_SMBUS_WORD_DATA:
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TXFIFO_WR(smbus, addr | MTXFIFO_START);
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TXFIFO_WR(smbus, command);
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if (read_write) {
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TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
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TXFIFO_WR(smbus, 2 | MTXFIFO_READ | MTXFIFO_STOP);
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} else {
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TXFIFO_WR(smbus, data->word & MTXFIFO_DATA_M);
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TXFIFO_WR(smbus, MTXFIFO_STOP | (data->word >> 8));
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}
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break;
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case I2C_SMBUS_BLOCK_DATA:
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TXFIFO_WR(smbus, addr | MTXFIFO_START);
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TXFIFO_WR(smbus, command);
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if (read_write) {
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TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
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TXFIFO_WR(smbus, 1 | MTXFIFO_READ);
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rd = RXFIFO_RD(smbus);
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len = min_t(u8, (rd & MRXFIFO_DATA_M),
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I2C_SMBUS_BLOCK_MAX);
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TXFIFO_WR(smbus, len | MTXFIFO_READ |
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MTXFIFO_STOP);
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} else {
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len = min_t(u8, data->block[0], I2C_SMBUS_BLOCK_MAX);
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TXFIFO_WR(smbus, len);
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for (i = 1; i < len; i++)
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TXFIFO_WR(smbus, data->block[i]);
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TXFIFO_WR(smbus, data->block[len] | MTXFIFO_STOP);
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}
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break;
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case I2C_SMBUS_PROC_CALL:
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read_write = I2C_SMBUS_READ;
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TXFIFO_WR(smbus, addr | MTXFIFO_START);
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TXFIFO_WR(smbus, command);
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TXFIFO_WR(smbus, data->word & MTXFIFO_DATA_M);
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TXFIFO_WR(smbus, (data->word >> 8) & MTXFIFO_DATA_M);
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TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
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TXFIFO_WR(smbus, 2 | MTXFIFO_STOP | MTXFIFO_READ);
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break;
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case I2C_SMBUS_BLOCK_PROC_CALL:
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len = min_t(u8, data->block[0], I2C_SMBUS_BLOCK_MAX - 1);
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read_write = I2C_SMBUS_READ;
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TXFIFO_WR(smbus, addr | MTXFIFO_START);
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TXFIFO_WR(smbus, command);
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TXFIFO_WR(smbus, len);
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for (i = 1; i <= len; i++)
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TXFIFO_WR(smbus, data->block[i]);
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TXFIFO_WR(smbus, addr | I2C_SMBUS_READ);
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TXFIFO_WR(smbus, MTXFIFO_READ | 1);
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rd = RXFIFO_RD(smbus);
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len = min_t(u8, (rd & MRXFIFO_DATA_M),
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I2C_SMBUS_BLOCK_MAX - len);
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TXFIFO_WR(smbus, len | MTXFIFO_READ | MTXFIFO_STOP);
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break;
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default:
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dev_warn(&adapter->dev, "Unsupported transaction %d\n", size);
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return -EINVAL;
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}
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err = pasemi_smb_waitready(smbus);
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if (err)
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goto reset_out;
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if (read_write == I2C_SMBUS_WRITE)
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return 0;
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switch (size) {
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case I2C_SMBUS_BYTE:
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case I2C_SMBUS_BYTE_DATA:
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rd = RXFIFO_RD(smbus);
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if (rd & MRXFIFO_EMPTY) {
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err = -ENODATA;
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goto reset_out;
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}
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data->byte = rd & MRXFIFO_DATA_M;
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break;
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case I2C_SMBUS_WORD_DATA:
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case I2C_SMBUS_PROC_CALL:
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rd = RXFIFO_RD(smbus);
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if (rd & MRXFIFO_EMPTY) {
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err = -ENODATA;
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goto reset_out;
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}
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data->word = rd & MRXFIFO_DATA_M;
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rd = RXFIFO_RD(smbus);
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if (rd & MRXFIFO_EMPTY) {
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err = -ENODATA;
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goto reset_out;
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}
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data->word |= (rd & MRXFIFO_DATA_M) << 8;
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break;
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case I2C_SMBUS_BLOCK_DATA:
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case I2C_SMBUS_BLOCK_PROC_CALL:
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data->block[0] = len;
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for (i = 1; i <= len; i ++) {
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rd = RXFIFO_RD(smbus);
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if (rd & MRXFIFO_EMPTY) {
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err = -ENODATA;
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goto reset_out;
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}
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data->block[i] = rd & MRXFIFO_DATA_M;
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}
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break;
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}
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return 0;
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reset_out:
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reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR |
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(CLK_100K_DIV & CTL_CLK_M)));
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return err;
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}
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static u32 pasemi_smb_func(struct i2c_adapter *adapter)
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{
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return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
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I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
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I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
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I2C_FUNC_SMBUS_BLOCK_PROC_CALL | I2C_FUNC_I2C;
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}
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static const struct i2c_algorithm smbus_algorithm = {
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.master_xfer = pasemi_i2c_xfer,
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.smbus_xfer = pasemi_smb_xfer,
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.functionality = pasemi_smb_func,
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};
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static int pasemi_smb_probe(struct pci_dev *dev,
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const struct pci_device_id *id)
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{
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struct pasemi_smbus *smbus;
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int error;
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if (!(pci_resource_flags(dev, 0) & IORESOURCE_IO))
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return -ENODEV;
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smbus = kzalloc(sizeof(struct pasemi_smbus), GFP_KERNEL);
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if (!smbus)
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return -ENOMEM;
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smbus->dev = dev;
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smbus->base = pci_resource_start(dev, 0);
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smbus->size = pci_resource_len(dev, 0);
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if (!request_region(smbus->base, smbus->size,
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pasemi_smb_driver.name)) {
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error = -EBUSY;
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goto out_kfree;
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}
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smbus->adapter.owner = THIS_MODULE;
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snprintf(smbus->adapter.name, sizeof(smbus->adapter.name),
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"PA Semi SMBus adapter at 0x%lx", smbus->base);
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smbus->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
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smbus->adapter.algo = &smbus_algorithm;
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smbus->adapter.algo_data = smbus;
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/* set up the sysfs linkage to our parent device */
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smbus->adapter.dev.parent = &dev->dev;
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reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR |
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(CLK_100K_DIV & CTL_CLK_M)));
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error = i2c_add_adapter(&smbus->adapter);
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if (error)
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goto out_release_region;
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pci_set_drvdata(dev, smbus);
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return 0;
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out_release_region:
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release_region(smbus->base, smbus->size);
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out_kfree:
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kfree(smbus);
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return error;
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}
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static void pasemi_smb_remove(struct pci_dev *dev)
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{
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struct pasemi_smbus *smbus = pci_get_drvdata(dev);
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i2c_del_adapter(&smbus->adapter);
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release_region(smbus->base, smbus->size);
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kfree(smbus);
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}
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static const struct pci_device_id pasemi_smb_ids[] = {
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{ PCI_DEVICE(0x1959, 0xa003) },
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{ 0, }
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};
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MODULE_DEVICE_TABLE(pci, pasemi_smb_ids);
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static struct pci_driver pasemi_smb_driver = {
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.name = "i2c-pasemi",
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.id_table = pasemi_smb_ids,
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.probe = pasemi_smb_probe,
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.remove = pasemi_smb_remove,
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};
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module_pci_driver(pasemi_smb_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
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MODULE_DESCRIPTION("PA Semi PWRficient SMBus driver");
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