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	Each ENETC PF has its own MDIO interface, the corresponding MDIO registers are mapped in the ENETC's Port register block. The current patch adds a driver for these PF level MDIO buses, so that each PF can manage directly its own external link. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
		
			
				
	
	
		
			199 lines
		
	
	
	
		
			4.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			199 lines
		
	
	
	
		
			4.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/* Copyright 2019 NXP */
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#include <linux/mdio.h>
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#include <linux/of_mdio.h>
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#include <linux/iopoll.h>
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#include <linux/of.h>
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#include "enetc_pf.h"
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struct enetc_mdio_regs {
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	u32	mdio_cfg;	/* MDIO configuration and status */
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	u32	mdio_ctl;	/* MDIO control */
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	u32	mdio_data;	/* MDIO data */
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	u32	mdio_addr;	/* MDIO address */
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};
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#define bus_to_enetc_regs(bus)	(struct enetc_mdio_regs __iomem *)((bus)->priv)
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#define ENETC_MDIO_REG_OFFSET	0x1c00
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#define ENETC_MDC_DIV		258
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#define MDIO_CFG_CLKDIV(x)	((((x) >> 1) & 0xff) << 8)
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#define MDIO_CFG_BSY		BIT(0)
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#define MDIO_CFG_RD_ER		BIT(1)
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#define MDIO_CFG_ENC45		BIT(6)
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 /* external MDIO only - driven on neg MDC edge */
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#define MDIO_CFG_NEG		BIT(23)
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#define MDIO_CTL_DEV_ADDR(x)	((x) & 0x1f)
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#define MDIO_CTL_PORT_ADDR(x)	(((x) & 0x1f) << 5)
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#define MDIO_CTL_READ		BIT(15)
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#define MDIO_DATA(x)		((x) & 0xffff)
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#define TIMEOUT	1000
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static int enetc_mdio_wait_complete(struct enetc_mdio_regs __iomem *regs)
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{
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	u32 val;
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	return readx_poll_timeout(enetc_rd_reg, ®s->mdio_cfg, val,
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				  !(val & MDIO_CFG_BSY), 10, 10 * TIMEOUT);
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}
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static int enetc_mdio_write(struct mii_bus *bus, int phy_id, int regnum,
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			    u16 value)
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{
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	struct enetc_mdio_regs __iomem *regs = bus_to_enetc_regs(bus);
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	u32 mdio_ctl, mdio_cfg;
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	u16 dev_addr;
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	int ret;
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	mdio_cfg = MDIO_CFG_CLKDIV(ENETC_MDC_DIV) | MDIO_CFG_NEG;
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	if (regnum & MII_ADDR_C45) {
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		dev_addr = (regnum >> 16) & 0x1f;
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		mdio_cfg |= MDIO_CFG_ENC45;
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	} else {
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		/* clause 22 (ie 1G) */
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		dev_addr = regnum & 0x1f;
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		mdio_cfg &= ~MDIO_CFG_ENC45;
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	}
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	enetc_wr_reg(®s->mdio_cfg, mdio_cfg);
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	ret = enetc_mdio_wait_complete(regs);
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	if (ret)
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		return ret;
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	/* set port and dev addr */
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	mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
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	enetc_wr_reg(®s->mdio_ctl, mdio_ctl);
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	/* set the register address */
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	if (regnum & MII_ADDR_C45) {
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		enetc_wr_reg(®s->mdio_addr, regnum & 0xffff);
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		ret = enetc_mdio_wait_complete(regs);
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		if (ret)
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			return ret;
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	}
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	/* write the value */
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	enetc_wr_reg(®s->mdio_data, MDIO_DATA(value));
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	ret = enetc_mdio_wait_complete(regs);
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	if (ret)
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		return ret;
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	return 0;
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}
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static int enetc_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
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{
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	struct enetc_mdio_regs __iomem *regs = bus_to_enetc_regs(bus);
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	u32 mdio_ctl, mdio_cfg;
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	u16 dev_addr, value;
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	int ret;
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	mdio_cfg = MDIO_CFG_CLKDIV(ENETC_MDC_DIV) | MDIO_CFG_NEG;
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	if (regnum & MII_ADDR_C45) {
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		dev_addr = (regnum >> 16) & 0x1f;
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		mdio_cfg |= MDIO_CFG_ENC45;
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	} else {
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		dev_addr = regnum & 0x1f;
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		mdio_cfg &= ~MDIO_CFG_ENC45;
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	}
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	enetc_wr_reg(®s->mdio_cfg, mdio_cfg);
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	ret = enetc_mdio_wait_complete(regs);
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	if (ret)
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		return ret;
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	/* set port and device addr */
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	mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
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	enetc_wr_reg(®s->mdio_ctl, mdio_ctl);
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	/* set the register address */
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	if (regnum & MII_ADDR_C45) {
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		enetc_wr_reg(®s->mdio_addr, regnum & 0xffff);
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		ret = enetc_mdio_wait_complete(regs);
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		if (ret)
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			return ret;
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	}
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	/* initiate the read */
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	enetc_wr_reg(®s->mdio_ctl, mdio_ctl | MDIO_CTL_READ);
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	ret = enetc_mdio_wait_complete(regs);
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	if (ret)
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		return ret;
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	/* return all Fs if nothing was there */
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	if (enetc_rd_reg(®s->mdio_cfg) & MDIO_CFG_RD_ER) {
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		dev_dbg(&bus->dev,
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			"Error while reading PHY%d reg at %d.%hhu\n",
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			phy_id, dev_addr, regnum);
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		return 0xffff;
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	}
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	value = enetc_rd_reg(®s->mdio_data) & 0xffff;
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	return value;
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}
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int enetc_mdio_probe(struct enetc_pf *pf)
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{
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	struct device *dev = &pf->si->pdev->dev;
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	struct enetc_mdio_regs __iomem *regs;
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	struct device_node *np;
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	struct mii_bus *bus;
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	int ret;
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	bus = mdiobus_alloc_size(sizeof(regs));
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	if (!bus)
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		return -ENOMEM;
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	bus->name = "Freescale ENETC MDIO Bus";
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	bus->read = enetc_mdio_read;
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	bus->write = enetc_mdio_write;
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	bus->parent = dev;
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	snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev));
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	/* store the enetc mdio base address for this bus */
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	regs = pf->si->hw.port + ENETC_MDIO_REG_OFFSET;
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	bus->priv = regs;
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	np = of_get_child_by_name(dev->of_node, "mdio");
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	if (!np) {
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		dev_err(dev, "MDIO node missing\n");
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		ret = -EINVAL;
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		goto err_registration;
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	}
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	ret = of_mdiobus_register(bus, np);
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	if (ret) {
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		of_node_put(np);
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		dev_err(dev, "cannot register MDIO bus\n");
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		goto err_registration;
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	}
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	of_node_put(np);
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	pf->mdio = bus;
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	return 0;
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err_registration:
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	mdiobus_free(bus);
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	return ret;
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}
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void enetc_mdio_remove(struct enetc_pf *pf)
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{
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	if (pf->mdio) {
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		mdiobus_unregister(pf->mdio);
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		mdiobus_free(pf->mdio);
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	}
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}
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