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c32759035a
This patch adds support for audio CODEC core of rk3328. Rockchip does not publish detail specification of this core but driver source code is opened on their GitHub repository. https://github.com/rockchip-linux/kernel So I ported this code to linux-next and added some trivial fixes. Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net> Signed-off-by: Mark Brown <broonie@kernel.org>
210 lines
6.4 KiB
C
210 lines
6.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* rk3328 ALSA SoC Audio driver
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*
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* Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd All rights reserved.
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*/
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#ifndef _RK3328_CODEC_H
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#define _RK3328_CODEC_H
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#include <linux/bitfield.h>
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/* codec register */
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#define CODEC_RESET (0x00 << 2)
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#define DAC_INIT_CTRL1 (0x03 << 2)
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#define DAC_INIT_CTRL2 (0x04 << 2)
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#define DAC_INIT_CTRL3 (0x05 << 2)
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#define DAC_PRECHARGE_CTRL (0x22 << 2)
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#define DAC_PWR_CTRL (0x23 << 2)
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#define DAC_CLK_CTRL (0x24 << 2)
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#define HPMIX_CTRL (0x25 << 2)
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#define DAC_SELECT (0x26 << 2)
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#define HPOUT_CTRL (0x27 << 2)
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#define HPOUTL_GAIN_CTRL (0x28 << 2)
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#define HPOUTR_GAIN_CTRL (0x29 << 2)
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#define HPOUT_POP_CTRL (0x2a << 2)
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/* REG00: CODEC_RESET */
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#define PWR_RST_BYPASS_DIS (0x0 << 6)
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#define PWR_RST_BYPASS_EN (0x1 << 6)
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#define DIG_CORE_RST (0x0 << 1)
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#define DIG_CORE_WORK (0x1 << 1)
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#define SYS_RST (0x0 << 0)
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#define SYS_WORK (0x1 << 0)
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/* REG03: DAC_INIT_CTRL1 */
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#define PIN_DIRECTION_MASK BIT(5)
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#define PIN_DIRECTION_IN (0x0 << 5)
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#define PIN_DIRECTION_OUT (0x1 << 5)
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#define DAC_I2S_MODE_MASK BIT(4)
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#define DAC_I2S_MODE_SLAVE (0x0 << 4)
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#define DAC_I2S_MODE_MASTER (0x1 << 4)
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/* REG04: DAC_INIT_CTRL2 */
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#define DAC_I2S_LRP_MASK BIT(7)
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#define DAC_I2S_LRP_NORMAL (0x0 << 7)
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#define DAC_I2S_LRP_REVERSAL (0x1 << 7)
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#define DAC_VDL_MASK GENMASK(6, 5)
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#define DAC_VDL_16BITS (0x0 << 5)
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#define DAC_VDL_20BITS (0x1 << 5)
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#define DAC_VDL_24BITS (0x2 << 5)
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#define DAC_VDL_32BITS (0x3 << 5)
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#define DAC_MODE_MASK GENMASK(4, 3)
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#define DAC_MODE_RJM (0x0 << 3)
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#define DAC_MODE_LJM (0x1 << 3)
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#define DAC_MODE_I2S (0x2 << 3)
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#define DAC_MODE_PCM (0x3 << 3)
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#define DAC_LR_SWAP_MASK BIT(2)
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#define DAC_LR_SWAP_DIS (0x0 << 2)
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#define DAC_LR_SWAP_EN (0x1 << 2)
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/* REG05: DAC_INIT_CTRL3 */
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#define DAC_WL_MASK GENMASK(3, 2)
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#define DAC_WL_16BITS (0x0 << 2)
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#define DAC_WL_20BITS (0x1 << 2)
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#define DAC_WL_24BITS (0x2 << 2)
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#define DAC_WL_32BITS (0x3 << 2)
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#define DAC_RST_MASK BIT(1)
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#define DAC_RST_EN (0x0 << 1)
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#define DAC_RST_DIS (0x1 << 1)
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#define DAC_BCP_MASK BIT(0)
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#define DAC_BCP_NORMAL (0x0 << 0)
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#define DAC_BCP_REVERSAL (0x1 << 0)
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/* REG22: DAC_PRECHARGE_CTRL */
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#define DAC_CHARGE_XCHARGE_MASK BIT(7)
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#define DAC_CHARGE_DISCHARGE (0x0 << 7)
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#define DAC_CHARGE_PRECHARGE (0x1 << 7)
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#define DAC_CHARGE_CURRENT_64I_MASK BIT(6)
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#define DAC_CHARGE_CURRENT_64I (0x1 << 6)
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#define DAC_CHARGE_CURRENT_32I_MASK BIT(5)
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#define DAC_CHARGE_CURRENT_32I (0x1 << 5)
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#define DAC_CHARGE_CURRENT_16I_MASK BIT(4)
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#define DAC_CHARGE_CURRENT_16I (0x1 << 4)
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#define DAC_CHARGE_CURRENT_08I_MASK BIT(3)
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#define DAC_CHARGE_CURRENT_08I (0x1 << 3)
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#define DAC_CHARGE_CURRENT_04I_MASK BIT(2)
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#define DAC_CHARGE_CURRENT_04I (0x1 << 2)
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#define DAC_CHARGE_CURRENT_02I_MASK BIT(1)
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#define DAC_CHARGE_CURRENT_02I (0x1 << 1)
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#define DAC_CHARGE_CURRENT_I_MASK BIT(0)
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#define DAC_CHARGE_CURRENT_I (0x1 << 0)
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#define DAC_CHARGE_CURRENT_ALL_MASK GENMASK(6, 0)
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#define DAC_CHARGE_CURRENT_ALL_OFF 0x00
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#define DAC_CHARGE_CURRENT_ALL_ON 0x7f
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/* REG23: DAC_PWR_CTRL */
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#define DAC_PWR_MASK BIT(6)
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#define DAC_PWR_OFF (0x0 << 6)
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#define DAC_PWR_ON (0x1 << 6)
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#define DACL_PATH_REFV_MASK BIT(5)
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#define DACL_PATH_REFV_OFF (0x0 << 5)
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#define DACL_PATH_REFV_ON (0x1 << 5)
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#define HPOUTL_ZERO_CROSSING_MASK BIT(4)
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#define HPOUTL_ZERO_CROSSING_OFF (0x0 << 4)
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#define HPOUTL_ZERO_CROSSING_ON (0x1 << 4)
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#define DACR_PATH_REFV_MASK BIT(1)
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#define DACR_PATH_REFV_OFF (0x0 << 1)
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#define DACR_PATH_REFV_ON (0x1 << 1)
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#define HPOUTR_ZERO_CROSSING_MASK BIT(0)
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#define HPOUTR_ZERO_CROSSING_OFF (0x0 << 0)
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#define HPOUTR_ZERO_CROSSING_ON (0x1 << 0)
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/* REG24: DAC_CLK_CTRL */
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#define DACL_REFV_MASK BIT(7)
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#define DACL_REFV_OFF (0x0 << 7)
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#define DACL_REFV_ON (0x1 << 7)
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#define DACL_CLK_MASK BIT(6)
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#define DACL_CLK_OFF (0x0 << 6)
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#define DACL_CLK_ON (0x1 << 6)
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#define DACL_MASK BIT(5)
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#define DACL_OFF (0x0 << 5)
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#define DACL_ON (0x1 << 5)
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#define DACL_INIT_MASK BIT(4)
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#define DACL_INIT_OFF (0x0 << 4)
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#define DACL_INIT_ON (0x1 << 4)
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#define DACR_REFV_MASK BIT(3)
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#define DACR_REFV_OFF (0x0 << 3)
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#define DACR_REFV_ON (0x1 << 3)
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#define DACR_CLK_MASK BIT(2)
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#define DACR_CLK_OFF (0x0 << 2)
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#define DACR_CLK_ON (0x1 << 2)
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#define DACR_MASK BIT(1)
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#define DACR_OFF (0x0 << 1)
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#define DACR_ON (0x1 << 1)
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#define DACR_INIT_MASK BIT(0)
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#define DACR_INIT_OFF (0x0 << 0)
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#define DACR_INIT_ON (0x1 << 0)
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/* REG25: HPMIX_CTRL*/
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#define HPMIXL_MASK BIT(6)
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#define HPMIXL_DIS (0x0 << 6)
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#define HPMIXL_EN (0x1 << 6)
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#define HPMIXL_INIT_MASK BIT(5)
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#define HPMIXL_INIT_DIS (0x0 << 5)
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#define HPMIXL_INIT_EN (0x1 << 5)
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#define HPMIXL_INIT2_MASK BIT(4)
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#define HPMIXL_INIT2_DIS (0x0 << 4)
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#define HPMIXL_INIT2_EN (0x1 << 4)
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#define HPMIXR_MASK BIT(2)
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#define HPMIXR_DIS (0x0 << 2)
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#define HPMIXR_EN (0x1 << 2)
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#define HPMIXR_INIT_MASK BIT(1)
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#define HPMIXR_INIT_DIS (0x0 << 1)
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#define HPMIXR_INIT_EN (0x1 << 1)
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#define HPMIXR_INIT2_MASK BIT(0)
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#define HPMIXR_INIT2_DIS (0x0 << 0)
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#define HPMIXR_INIT2_EN (0x1 << 0)
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/* REG26: DAC_SELECT */
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#define DACL_SELECT_MASK BIT(4)
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#define DACL_UNSELECT (0x0 << 4)
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#define DACL_SELECT (0x1 << 4)
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#define DACR_SELECT_MASK BIT(0)
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#define DACR_UNSELECT (0x0 << 0)
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#define DACR_SELECT (0x1 << 0)
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/* REG27: HPOUT_CTRL */
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#define HPOUTL_MASK BIT(7)
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#define HPOUTL_DIS (0x0 << 7)
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#define HPOUTL_EN (0x1 << 7)
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#define HPOUTL_INIT_MASK BIT(6)
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#define HPOUTL_INIT_DIS (0x0 << 6)
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#define HPOUTL_INIT_EN (0x1 << 6)
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#define HPOUTL_MUTE_MASK BIT(5)
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#define HPOUTL_MUTE (0x0 << 5)
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#define HPOUTL_UNMUTE (0x1 << 5)
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#define HPOUTR_MASK BIT(4)
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#define HPOUTR_DIS (0x0 << 4)
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#define HPOUTR_EN (0x1 << 4)
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#define HPOUTR_INIT_MASK BIT(3)
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#define HPOUTR_INIT_DIS (0x0 << 3)
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#define HPOUTR_INIT_EN (0x1 << 3)
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#define HPOUTR_MUTE_MASK BIT(2)
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#define HPOUTR_MUTE (0x0 << 2)
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#define HPOUTR_UNMUTE (0x1 << 2)
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/* REG28: HPOUTL_GAIN_CTRL */
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#define HPOUTL_GAIN_MASK GENMASK(4, 0)
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/* REG29: HPOUTR_GAIN_CTRL */
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#define HPOUTR_GAIN_MASK GENMASK(4, 0)
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/* REG2a: HPOUT_POP_CTRL */
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#define HPOUTR_POP_MASK GENMASK(5, 4)
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#define HPOUTR_POP_XCHARGE (0x1 << 4)
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#define HPOUTR_POP_WORK (0x2 << 4)
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#define HPOUTL_POP_MASK GENMASK(1, 0)
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#define HPOUTL_POP_XCHARGE (0x1 << 0)
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#define HPOUTL_POP_WORK (0x2 << 0)
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#define RK3328_HIFI 0
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struct rk3328_reg_msk_val {
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unsigned int reg;
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unsigned int msk;
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unsigned int val;
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};
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#endif
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