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18f90d372c
Since those were introduced in:c8ce48f065("asm-generic: Make time32 syscall numbers optional") But when the asm-generic/unistd.h was sync'ed with tools/ in:1a787fc5ba("tools headers uapi: Sync copy of asm-generic/unistd.h with the kernel sources") I forgot to copy the files for the architectures that define __ARCH_WANT_TIME32_SYSCALLS, so the perf build was breaking there, as reported by Vineet Gupta for the ARC architecture. After updating my ARC container to use the glibc based toolchain + cross building libnuma, zlib and elfutils, I finally managed to reproduce the problem and verify that this now is fixed and will not regress as will be tested before each pull req sent upstream. Reported-by: Vineet Gupta <Vineet.Gupta1@synopsys.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Jiri Olsa <jolsa@kernel.org> CC: linux-snps-arc@lists.infradead.org Cc: Namhyung Kim <namhyung@kernel.org> Link: https://lkml.kernel.org/r/20190426193531.GC28586@kernel.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
42 lines
1.8 KiB
C
42 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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* Copyright (C) 2018 David Abdurachmanov <david.abdurachmanov@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifdef __LP64__
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#define __ARCH_WANT_NEW_STAT
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#define __ARCH_WANT_SET_GET_RLIMIT
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#endif /* __LP64__ */
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#include <asm-generic/unistd.h>
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/*
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* Allows the instruction cache to be flushed from userspace. Despite RISC-V
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* having a direct 'fence.i' instruction available to userspace (which we
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* can't trap!), that's not actually viable when running on Linux because the
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* kernel might schedule a process on another hart. There is no way for
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* userspace to handle this without invoking the kernel (as it doesn't know the
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* thread->hart mappings), so we've defined a RISC-V specific system call to
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* flush the instruction cache.
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*
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* __NR_riscv_flush_icache is defined to flush the instruction cache over an
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* address range, with the flush applying to either all threads or just the
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* caller. We don't currently do anything with the address range, that's just
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* in there for forwards compatibility.
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*/
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#ifndef __NR_riscv_flush_icache
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#define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15)
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#endif
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__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache)
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