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Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
114 lines
2.4 KiB
C
114 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*/
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#include <linux/irqchip.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
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#include <linux/of_platform.h>
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#include <linux/phy.h>
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#include <linux/regmap.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include "common.h"
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static int ar8031_phy_fixup(struct phy_device *dev)
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{
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u16 val;
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/* Set RGMII IO voltage to 1.8V */
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phy_write(dev, 0x1d, 0x1f);
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phy_write(dev, 0x1e, 0x8);
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/* disable phy AR8031 SmartEEE function. */
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phy_write(dev, 0xd, 0x3);
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phy_write(dev, 0xe, 0x805d);
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phy_write(dev, 0xd, 0x4003);
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val = phy_read(dev, 0xe);
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val &= ~(0x1 << 8);
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phy_write(dev, 0xe, val);
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/* introduce tx clock delay */
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phy_write(dev, 0x1d, 0x5);
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val = phy_read(dev, 0x1e);
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val |= 0x0100;
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phy_write(dev, 0x1e, val);
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return 0;
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}
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static int bcm54220_phy_fixup(struct phy_device *dev)
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{
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/* enable RXC skew select RGMII copper mode */
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phy_write(dev, 0x1e, 0x21);
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phy_write(dev, 0x1f, 0x7ea8);
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phy_write(dev, 0x1e, 0x2f);
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phy_write(dev, 0x1f, 0x71b7);
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return 0;
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}
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#define PHY_ID_AR8031 0x004dd074
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#define PHY_ID_BCM54220 0x600d8589
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static void __init imx7d_enet_phy_init(void)
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{
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if (IS_BUILTIN(CONFIG_PHYLIB)) {
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phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
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ar8031_phy_fixup);
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phy_register_fixup_for_uid(PHY_ID_BCM54220, 0xffffffff,
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bcm54220_phy_fixup);
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}
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}
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static void __init imx7d_enet_clk_sel(void)
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{
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struct regmap *gpr;
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gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr");
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if (!IS_ERR(gpr)) {
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regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0);
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regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0);
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} else {
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pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n");
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}
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}
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static inline void imx7d_enet_init(void)
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{
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imx7d_enet_phy_init();
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imx7d_enet_clk_sel();
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}
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static void __init imx7d_init_machine(void)
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{
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struct device *parent;
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parent = imx_soc_device_init();
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if (parent == NULL)
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pr_warn("failed to initialize soc device\n");
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imx_anatop_init();
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imx7d_enet_init();
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}
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static void __init imx7d_init_irq(void)
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{
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imx_init_revision_from_anatop();
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imx_src_init();
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irqchip_init();
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}
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static const char *const imx7d_dt_compat[] __initconst = {
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"fsl,imx7d",
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"fsl,imx7s",
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NULL,
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};
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DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual (Device Tree)")
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.init_irq = imx7d_init_irq,
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.init_machine = imx7d_init_machine,
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.dt_compat = imx7d_dt_compat,
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MACHINE_END
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