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4d5a91fd1f
In case of error, the function devm_ioremap_resource() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check should
be replaced with IS_ERR().
Fixes: f24fcff1d2 ("hwspinlock: add STM32 hwspinlock device")
Acked-by: Benjamin Gaignard <benjamin.gaignard@gmail.com>
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
156 lines
3.8 KiB
C
156 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) STMicroelectronics SA 2018
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* Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
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*/
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#include <linux/clk.h>
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#include <linux/hwspinlock.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include "hwspinlock_internal.h"
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#define STM32_MUTEX_COREID BIT(8)
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#define STM32_MUTEX_LOCK_BIT BIT(31)
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#define STM32_MUTEX_NUM_LOCKS 32
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struct stm32_hwspinlock {
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struct clk *clk;
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struct hwspinlock_device bank;
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};
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static int stm32_hwspinlock_trylock(struct hwspinlock *lock)
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{
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void __iomem *lock_addr = lock->priv;
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u32 status;
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writel(STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID, lock_addr);
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status = readl(lock_addr);
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return status == (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID);
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}
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static void stm32_hwspinlock_unlock(struct hwspinlock *lock)
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{
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void __iomem *lock_addr = lock->priv;
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writel(STM32_MUTEX_COREID, lock_addr);
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}
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static const struct hwspinlock_ops stm32_hwspinlock_ops = {
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.trylock = stm32_hwspinlock_trylock,
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.unlock = stm32_hwspinlock_unlock,
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};
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static int stm32_hwspinlock_probe(struct platform_device *pdev)
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{
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struct stm32_hwspinlock *hw;
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void __iomem *io_base;
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struct resource *res;
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size_t array_size;
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int i, ret;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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io_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(io_base))
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return PTR_ERR(io_base);
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array_size = STM32_MUTEX_NUM_LOCKS * sizeof(struct hwspinlock);
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hw = devm_kzalloc(&pdev->dev, sizeof(*hw) + array_size, GFP_KERNEL);
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if (!hw)
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return -ENOMEM;
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hw->clk = devm_clk_get(&pdev->dev, "hsem");
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if (IS_ERR(hw->clk))
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return PTR_ERR(hw->clk);
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for (i = 0; i < STM32_MUTEX_NUM_LOCKS; i++)
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hw->bank.lock[i].priv = io_base + i * sizeof(u32);
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platform_set_drvdata(pdev, hw);
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pm_runtime_enable(&pdev->dev);
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ret = hwspin_lock_register(&hw->bank, &pdev->dev, &stm32_hwspinlock_ops,
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0, STM32_MUTEX_NUM_LOCKS);
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if (ret)
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pm_runtime_disable(&pdev->dev);
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return ret;
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}
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static int stm32_hwspinlock_remove(struct platform_device *pdev)
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{
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struct stm32_hwspinlock *hw = platform_get_drvdata(pdev);
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int ret;
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ret = hwspin_lock_unregister(&hw->bank);
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if (ret)
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dev_err(&pdev->dev, "%s failed: %d\n", __func__, ret);
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pm_runtime_disable(&pdev->dev);
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return 0;
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}
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static int __maybe_unused stm32_hwspinlock_runtime_suspend(struct device *dev)
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{
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struct stm32_hwspinlock *hw = dev_get_drvdata(dev);
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clk_disable_unprepare(hw->clk);
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return 0;
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}
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static int __maybe_unused stm32_hwspinlock_runtime_resume(struct device *dev)
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{
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struct stm32_hwspinlock *hw = dev_get_drvdata(dev);
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clk_prepare_enable(hw->clk);
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return 0;
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}
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static const struct dev_pm_ops stm32_hwspinlock_pm_ops = {
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SET_RUNTIME_PM_OPS(stm32_hwspinlock_runtime_suspend,
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stm32_hwspinlock_runtime_resume,
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NULL)
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};
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static const struct of_device_id stm32_hwpinlock_ids[] = {
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{ .compatible = "st,stm32-hwspinlock", },
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{},
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};
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MODULE_DEVICE_TABLE(of, stm32_hwpinlock_ids);
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static struct platform_driver stm32_hwspinlock_driver = {
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.probe = stm32_hwspinlock_probe,
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.remove = stm32_hwspinlock_remove,
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.driver = {
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.name = "stm32_hwspinlock",
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.of_match_table = stm32_hwpinlock_ids,
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.pm = &stm32_hwspinlock_pm_ops,
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},
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};
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static int __init stm32_hwspinlock_init(void)
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{
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return platform_driver_register(&stm32_hwspinlock_driver);
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}
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/* board init code might need to reserve hwspinlocks for predefined purposes */
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postcore_initcall(stm32_hwspinlock_init);
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static void __exit stm32_hwspinlock_exit(void)
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{
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platform_driver_unregister(&stm32_hwspinlock_driver);
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}
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module_exit(stm32_hwspinlock_exit);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Hardware spinlock driver for STM32 SoCs");
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MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
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