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When building with W=1:
CC arch/m68k/coldfire/intc.o
arch/m68k/coldfire/intc.c:83:6: warning: no previous prototype for ‘mcf_maskimr’ [-Wmissing-prototypes]
void mcf_maskimr(unsigned int mask)
^~~~~~~~~~~
The mcf_maskimr() function is only used within this file, make it static
to reduce name space pollution and fix warning.
Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
150 lines
3.4 KiB
C
150 lines
3.4 KiB
C
/*
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* intc.c -- support for the old ColdFire interrupt controller
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*
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* (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/traps.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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/*
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* The mapping of irq number to a mask register bit is not one-to-one.
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* The irq numbers are either based on "level" of interrupt or fixed
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* for an autovector-able interrupt. So we keep a local data structure
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* that maps from irq to mask register. Not all interrupts will have
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* an IMR bit.
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*/
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unsigned char mcf_irq2imr[NR_IRQS];
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/*
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* Define the minimum and maximum external interrupt numbers.
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* This is also used as the "level" interrupt numbers.
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*/
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#define EIRQ1 25
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#define EIRQ7 31
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/*
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* In the early version 2 core ColdFire parts the IMR register was 16 bits
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* in size. Version 3 (and later version 2) core parts have a 32 bit
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* sized IMR register. Provide some size independent methods to access the
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* IMR register.
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*/
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#ifdef MCFSIM_IMR_IS_16BITS
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void mcf_setimr(int index)
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{
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u16 imr;
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imr = __raw_readw(MCFSIM_IMR);
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__raw_writew(imr | (0x1 << index), MCFSIM_IMR);
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}
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void mcf_clrimr(int index)
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{
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u16 imr;
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imr = __raw_readw(MCFSIM_IMR);
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__raw_writew(imr & ~(0x1 << index), MCFSIM_IMR);
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}
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static void mcf_maskimr(unsigned int mask)
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{
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u16 imr;
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imr = __raw_readw(MCFSIM_IMR);
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imr |= mask;
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__raw_writew(imr, MCFSIM_IMR);
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}
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#else
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void mcf_setimr(int index)
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{
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u32 imr;
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imr = __raw_readl(MCFSIM_IMR);
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__raw_writel(imr | (0x1 << index), MCFSIM_IMR);
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}
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void mcf_clrimr(int index)
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{
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u32 imr;
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imr = __raw_readl(MCFSIM_IMR);
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__raw_writel(imr & ~(0x1 << index), MCFSIM_IMR);
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}
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static void mcf_maskimr(unsigned int mask)
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{
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u32 imr;
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imr = __raw_readl(MCFSIM_IMR);
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imr |= mask;
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__raw_writel(imr, MCFSIM_IMR);
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}
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#endif
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/*
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* Interrupts can be "vectored" on the ColdFire cores that support this old
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* interrupt controller. That is, the device raising the interrupt can also
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* supply the vector number to interrupt through. The AVR register of the
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* interrupt controller enables or disables this for each external interrupt,
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* so provide generic support for this. Setting this up is out-of-band for
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* the interrupt system API's, and needs to be done by the driver that
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* supports this device. Very few devices actually use this.
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*/
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void mcf_autovector(int irq)
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{
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#ifdef MCFSIM_AVR
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if ((irq >= EIRQ1) && (irq <= EIRQ7)) {
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u8 avec;
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avec = __raw_readb(MCFSIM_AVR);
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avec |= (0x1 << (irq - EIRQ1 + 1));
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__raw_writeb(avec, MCFSIM_AVR);
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}
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#endif
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}
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static void intc_irq_mask(struct irq_data *d)
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{
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if (mcf_irq2imr[d->irq])
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mcf_setimr(mcf_irq2imr[d->irq]);
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}
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static void intc_irq_unmask(struct irq_data *d)
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{
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if (mcf_irq2imr[d->irq])
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mcf_clrimr(mcf_irq2imr[d->irq]);
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}
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static int intc_irq_set_type(struct irq_data *d, unsigned int type)
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{
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return 0;
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}
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static struct irq_chip intc_irq_chip = {
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.name = "CF-INTC",
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.irq_mask = intc_irq_mask,
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.irq_unmask = intc_irq_unmask,
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.irq_set_type = intc_irq_set_type,
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};
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void __init init_IRQ(void)
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{
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int irq;
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mcf_maskimr(0xffffffff);
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for (irq = 0; (irq < NR_IRQS); irq++) {
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irq_set_chip(irq, &intc_irq_chip);
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irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
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irq_set_handler(irq, handle_level_irq);
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}
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}
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