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d428032b35
Add (and export) __cmpxchg_u16(), teach __cmpxchg() to use it. And get rid of manual truncation down to u8, etc. in there - the only reason for those is to avoid bogus warnings about constant truncation from sparse, and those are easy to avoid by turning that switch into conditional expression. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Paul E. McKenney <paulmck@kernel.org>
75 lines
1.6 KiB
C
75 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* bitops.c: atomic operations which got too long to be inlined all over
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* the place.
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*
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* Copyright 1999 Philipp Rumpf (prumpf@tux.org)
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* Copyright 2000 Grant Grundler (grundler@cup.hp.com)
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*/
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/atomic.h>
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#ifdef CONFIG_SMP
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arch_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned = {
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[0 ... (ATOMIC_HASH_SIZE-1)] = __ARCH_SPIN_LOCK_UNLOCKED
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};
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#endif
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#ifdef CONFIG_64BIT
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unsigned long notrace __xchg64(unsigned long x, volatile unsigned long *ptr)
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{
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unsigned long temp, flags;
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_atomic_spin_lock_irqsave(ptr, flags);
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temp = *ptr;
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*ptr = x;
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_atomic_spin_unlock_irqrestore(ptr, flags);
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return temp;
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}
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#endif
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unsigned long notrace __xchg32(int x, volatile int *ptr)
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{
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unsigned long flags;
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long temp;
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_atomic_spin_lock_irqsave(ptr, flags);
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temp = (long) *ptr; /* XXX - sign extension wanted? */
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*ptr = x;
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_atomic_spin_unlock_irqrestore(ptr, flags);
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return (unsigned long)temp;
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}
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unsigned long notrace __xchg8(char x, volatile char *ptr)
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{
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unsigned long flags;
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long temp;
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_atomic_spin_lock_irqsave(ptr, flags);
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temp = (long) *ptr; /* XXX - sign extension wanted? */
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*ptr = x;
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_atomic_spin_unlock_irqrestore(ptr, flags);
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return (unsigned long)temp;
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}
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#define CMPXCHG(T) \
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T notrace __cmpxchg_##T(volatile T *ptr, T old, T new) \
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{ \
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unsigned long flags; \
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T prev; \
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\
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_atomic_spin_lock_irqsave(ptr, flags); \
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if ((prev = *ptr) == old) \
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*ptr = new; \
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_atomic_spin_unlock_irqrestore(ptr, flags); \
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return prev; \
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}
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CMPXCHG(u64)
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CMPXCHG(u32)
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CMPXCHG(u16)
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CMPXCHG(u8)
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