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648c7fb16f
Make the architecture-optimized CRC code do its CPU feature checks in subsys_initcalls instead of arch_initcalls. This makes it consistent with arch/*/lib/crypto/ and ensures that it runs after initcalls that possibly could be a prerequisite for kernel-mode FPU, such as x86's xfd_update_static_branch() and loongarch's init_euen_mask(). Note: as far as I can tell, x86's xfd_update_static_branch() isn't *actually* needed for kernel-mode FPU. loongarch's init_euen_mask() is needed to enable save/restore of the vector registers, but loongarch doesn't yet have any CRC or crypto code that uses vector registers anyway. Regardless, let's be consistent with arch/*/lib/crypto/ and robust against any potential future dependency on an arch_initcall. Link: https://lore.kernel.org/r/20250510035959.87995-1-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@google.com>
111 lines
2.7 KiB
C
111 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* x86-optimized CRC32 functions
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*
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* Copyright (C) 2008 Intel Corporation
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* Copyright 2012 Xyratex Technology Limited
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* Copyright 2024 Google LLC
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*/
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#include <linux/crc32.h>
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#include <linux/module.h>
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#include "crc-pclmul-template.h"
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static __ro_after_init DEFINE_STATIC_KEY_FALSE(have_crc32);
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static __ro_after_init DEFINE_STATIC_KEY_FALSE(have_pclmulqdq);
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DECLARE_CRC_PCLMUL_FUNCS(crc32_lsb, u32);
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u32 crc32_le_arch(u32 crc, const u8 *p, size_t len)
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{
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CRC_PCLMUL(crc, p, len, crc32_lsb, crc32_lsb_0xedb88320_consts,
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have_pclmulqdq);
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return crc32_le_base(crc, p, len);
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}
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EXPORT_SYMBOL(crc32_le_arch);
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#ifdef CONFIG_X86_64
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#define CRC32_INST "crc32q %1, %q0"
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#else
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#define CRC32_INST "crc32l %1, %0"
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#endif
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/*
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* Use carryless multiply version of crc32c when buffer size is >= 512 to
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* account for FPU state save/restore overhead.
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*/
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#define CRC32C_PCLMUL_BREAKEVEN 512
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asmlinkage u32 crc32c_x86_3way(u32 crc, const u8 *buffer, size_t len);
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u32 crc32c_arch(u32 crc, const u8 *p, size_t len)
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{
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size_t num_longs;
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if (!static_branch_likely(&have_crc32))
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return crc32c_base(crc, p, len);
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if (IS_ENABLED(CONFIG_X86_64) && len >= CRC32C_PCLMUL_BREAKEVEN &&
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static_branch_likely(&have_pclmulqdq) && crypto_simd_usable()) {
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kernel_fpu_begin();
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crc = crc32c_x86_3way(crc, p, len);
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kernel_fpu_end();
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return crc;
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}
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for (num_longs = len / sizeof(unsigned long);
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num_longs != 0; num_longs--, p += sizeof(unsigned long))
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asm(CRC32_INST : "+r" (crc) : ASM_INPUT_RM (*(unsigned long *)p));
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if (sizeof(unsigned long) > 4 && (len & 4)) {
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asm("crc32l %1, %0" : "+r" (crc) : ASM_INPUT_RM (*(u32 *)p));
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p += 4;
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}
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if (len & 2) {
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asm("crc32w %1, %0" : "+r" (crc) : ASM_INPUT_RM (*(u16 *)p));
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p += 2;
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}
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if (len & 1)
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asm("crc32b %1, %0" : "+r" (crc) : ASM_INPUT_RM (*p));
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return crc;
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}
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EXPORT_SYMBOL(crc32c_arch);
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u32 crc32_be_arch(u32 crc, const u8 *p, size_t len)
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{
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return crc32_be_base(crc, p, len);
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}
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EXPORT_SYMBOL(crc32_be_arch);
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static int __init crc32_x86_init(void)
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{
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if (boot_cpu_has(X86_FEATURE_XMM4_2))
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static_branch_enable(&have_crc32);
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if (boot_cpu_has(X86_FEATURE_PCLMULQDQ)) {
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static_branch_enable(&have_pclmulqdq);
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INIT_CRC_PCLMUL(crc32_lsb);
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}
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return 0;
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}
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subsys_initcall(crc32_x86_init);
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static void __exit crc32_x86_exit(void)
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{
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}
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module_exit(crc32_x86_exit);
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u32 crc32_optimizations(void)
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{
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u32 optimizations = 0;
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if (static_key_enabled(&have_crc32))
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optimizations |= CRC32C_OPTIMIZATION;
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if (static_key_enabled(&have_pclmulqdq))
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optimizations |= CRC32_LE_OPTIMIZATION;
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return optimizations;
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}
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EXPORT_SYMBOL(crc32_optimizations);
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MODULE_DESCRIPTION("x86-optimized CRC32 functions");
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MODULE_LICENSE("GPL");
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