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ac8fd122e0
request_irq() is preferred over setup_irq(). Invocations of setup_irq() occur after memory allocators are ready. Per tglx[1], setup_irq() existed in olden days when allocators were not ready by the time early interrupts were initialized. Hence replace setup_irq() by request_irq(). remove_irq() has been replaced by free_irq() as well. There were build error's during previous version, couple of which was reported by kbuild test robot <lkp@intel.com> of which one was reported by Thomas Bogendoerfer <tsbogend@alpha.franken.de> as well. There were a few more issues including build errors, those also have been fixed. [1] https://lkml.kernel.org/r/alpine.DEB.2.20.1710191609480.1971@nanos Signed-off-by: afzal mohammed <afzal.mohd.ma@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
165 lines
4 KiB
C
165 lines
4 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
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*/
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mach-ar7/ar7.h>
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#define EXCEPT_OFFSET 0x80
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#define PACE_OFFSET 0xA0
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#define CHNLS_OFFSET 0x200
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#define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10)
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#define SEC_REG_OFFSET(reg) (EXCEPT_OFFSET + reg * 0x8)
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#define SEC_SR_OFFSET (SEC_REG_OFFSET(0)) /* 0x80 */
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#define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */
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#define SEC_CR_OFFSET (SEC_REG_OFFSET(1)) /* 0x88 */
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#define ESR_OFFSET(irq) (REG_OFFSET(irq, 2)) /* 0x20 */
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#define SEC_ESR_OFFSET (SEC_REG_OFFSET(2)) /* 0x90 */
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#define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) /* 0x30 */
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#define SEC_ECR_OFFSET (SEC_REG_OFFSET(3)) /* 0x98 */
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#define PIR_OFFSET (0x40)
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#define MSR_OFFSET (0x44)
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#define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */
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#define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */
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#define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr))
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#define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4))
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static int ar7_irq_base;
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static void ar7_unmask_irq(struct irq_data *d)
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{
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writel(1 << ((d->irq - ar7_irq_base) % 32),
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REG(ESR_OFFSET(d->irq - ar7_irq_base)));
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}
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static void ar7_mask_irq(struct irq_data *d)
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{
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writel(1 << ((d->irq - ar7_irq_base) % 32),
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REG(ECR_OFFSET(d->irq - ar7_irq_base)));
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}
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static void ar7_ack_irq(struct irq_data *d)
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{
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writel(1 << ((d->irq - ar7_irq_base) % 32),
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REG(CR_OFFSET(d->irq - ar7_irq_base)));
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}
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static void ar7_unmask_sec_irq(struct irq_data *d)
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{
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writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET));
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}
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static void ar7_mask_sec_irq(struct irq_data *d)
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{
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writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET));
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}
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static void ar7_ack_sec_irq(struct irq_data *d)
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{
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writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET));
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}
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static struct irq_chip ar7_irq_type = {
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.name = "AR7",
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.irq_unmask = ar7_unmask_irq,
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.irq_mask = ar7_mask_irq,
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.irq_ack = ar7_ack_irq
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};
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static struct irq_chip ar7_sec_irq_type = {
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.name = "AR7",
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.irq_unmask = ar7_unmask_sec_irq,
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.irq_mask = ar7_mask_sec_irq,
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.irq_ack = ar7_ack_sec_irq,
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};
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static void __init ar7_irq_init(int base)
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{
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int i;
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/*
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* Disable interrupts and clear pending
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*/
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writel(0xffffffff, REG(ECR_OFFSET(0)));
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writel(0xff, REG(ECR_OFFSET(32)));
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writel(0xffffffff, REG(SEC_ECR_OFFSET));
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writel(0xffffffff, REG(CR_OFFSET(0)));
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writel(0xff, REG(CR_OFFSET(32)));
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writel(0xffffffff, REG(SEC_CR_OFFSET));
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ar7_irq_base = base;
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for (i = 0; i < 40; i++) {
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writel(i, REG(CHNL_OFFSET(i)));
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/* Primary IRQ's */
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irq_set_chip_and_handler(base + i, &ar7_irq_type,
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handle_level_irq);
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/* Secondary IRQ's */
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if (i < 32)
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irq_set_chip_and_handler(base + i + 40,
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&ar7_sec_irq_type,
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handle_level_irq);
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}
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if (request_irq(2, no_action, IRQF_NO_THREAD, "AR7 cascade interrupt",
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NULL))
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pr_err("Failed to request irq 2 (AR7 cascade interrupt)\n");
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if (request_irq(ar7_irq_base, no_action, IRQF_NO_THREAD,
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"AR7 cascade interrupt", NULL)) {
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pr_err("Failed to request irq %d (AR7 cascade interrupt)\n",
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ar7_irq_base);
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}
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set_c0_status(IE_IRQ0);
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}
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void __init arch_init_irq(void)
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{
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mips_cpu_irq_init();
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ar7_irq_init(8);
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}
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static void ar7_cascade(void)
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{
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u32 status;
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int i, irq;
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/* Primary IRQ's */
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irq = readl(REG(PIR_OFFSET)) & 0x3f;
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if (irq) {
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do_IRQ(ar7_irq_base + irq);
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return;
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}
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/* Secondary IRQ's are cascaded through primary '0' */
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writel(1, REG(CR_OFFSET(irq)));
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status = readl(REG(SEC_SR_OFFSET));
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for (i = 0; i < 32; i++) {
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if (status & 1) {
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do_IRQ(ar7_irq_base + i + 40);
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return;
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}
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status >>= 1;
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}
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spurious_interrupt();
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
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if (pending & STATUSF_IP7) /* cpu timer */
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do_IRQ(7);
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else if (pending & STATUSF_IP2) /* int0 hardware line */
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ar7_cascade();
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else
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spurious_interrupt();
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}
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