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There are 4 lanes in each J7200 SERDES. Each SERDES lane mux can select upto 4 different IPs. Define all the possible functions. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Peter Rosin <peda@axentia.se> Cc: Peter Rosin <peda@axentia.se> Link: https://lore.kernel.org/r/20200930122032.23481-2-rogerq@ti.com
93 lines
3 KiB
C
93 lines
3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* This header provides constants for SERDES MUX for TI SoCs
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*/
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#ifndef _DT_BINDINGS_MUX_TI_SERDES
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#define _DT_BINDINGS_MUX_TI_SERDES
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/* J721E */
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#define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0
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#define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1
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#define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2
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#define J721E_SERDES0_LANE0_IP4_UNUSED 0x3
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#define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0
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#define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1
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#define J721E_SERDES0_LANE1_USB3_0 0x2
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#define J721E_SERDES0_LANE1_IP4_UNUSED 0x3
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#define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0
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#define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1
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#define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2
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#define J721E_SERDES1_LANE0_SGMII_LANE0 0x3
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#define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0
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#define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1
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#define J721E_SERDES1_LANE1_USB3_1 0x2
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#define J721E_SERDES1_LANE1_SGMII_LANE1 0x3
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#define J721E_SERDES2_LANE0_IP1_UNUSED 0x0
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#define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1
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#define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2
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#define J721E_SERDES2_LANE0_SGMII_LANE0 0x3
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#define J721E_SERDES2_LANE1_IP1_UNUSED 0x0
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#define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1
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#define J721E_SERDES2_LANE1_USB3_1 0x2
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#define J721E_SERDES2_LANE1_SGMII_LANE1 0x3
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#define J721E_SERDES3_LANE0_IP1_UNUSED 0x0
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#define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1
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#define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2
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#define J721E_SERDES3_LANE0_IP4_UNUSED 0x3
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#define J721E_SERDES3_LANE1_IP1_UNUSED 0x0
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#define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1
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#define J721E_SERDES3_LANE1_USB3_0 0x2
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#define J721E_SERDES3_LANE1_IP4_UNUSED 0x3
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#define J721E_SERDES4_LANE0_EDP_LANE0 0x0
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#define J721E_SERDES4_LANE0_IP2_UNUSED 0x1
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#define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2
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#define J721E_SERDES4_LANE0_IP4_UNUSED 0x3
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#define J721E_SERDES4_LANE1_EDP_LANE1 0x0
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#define J721E_SERDES4_LANE1_IP2_UNUSED 0x1
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#define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2
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#define J721E_SERDES4_LANE1_IP4_UNUSED 0x3
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#define J721E_SERDES4_LANE2_EDP_LANE2 0x0
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#define J721E_SERDES4_LANE2_IP2_UNUSED 0x1
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#define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2
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#define J721E_SERDES4_LANE2_IP4_UNUSED 0x3
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#define J721E_SERDES4_LANE3_EDP_LANE3 0x0
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#define J721E_SERDES4_LANE3_IP2_UNUSED 0x1
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#define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2
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#define J721E_SERDES4_LANE3_IP4_UNUSED 0x3
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/* J7200 */
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#define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0
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#define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1
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#define J7200_SERDES0_LANE0_IP3_UNUSED 0x2
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#define J7200_SERDES0_LANE0_IP4_UNUSED 0x3
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#define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0
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#define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1
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#define J7200_SERDES0_LANE1_IP3_UNUSED 0x2
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#define J7200_SERDES0_LANE1_IP4_UNUSED 0x3
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#define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0
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#define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1
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#define J7200_SERDES0_LANE2_IP3_UNUSED 0x2
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#define J7200_SERDES0_LANE2_IP4_UNUSED 0x3
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#define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0
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#define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1
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#define J7200_SERDES0_LANE3_USB 0x2
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#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3
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#endif /* _DT_BINDINGS_MUX_TI_SERDES */
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