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72c148d776
Aldebaran has different register mask definitions for regiter MC_VM_XGMI_LFB_CNTL. Use the correct masks to interpret fields of this register. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
111 lines
3.6 KiB
C
111 lines
3.6 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "gfxhub_v1_1.h"
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#include "gc/gc_9_2_1_offset.h"
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#include "gc/gc_9_2_1_sh_mask.h"
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#include "soc15_common.h"
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#define mmMC_VM_XGMI_LFB_CNTL_ALDE 0x0978
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#define mmMC_VM_XGMI_LFB_CNTL_ALDE_BASE_IDX 0
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#define mmMC_VM_XGMI_LFB_SIZE_ALDE 0x0979
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#define mmMC_VM_XGMI_LFB_SIZE_ALDE_BASE_IDX 0
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//MC_VM_XGMI_LFB_CNTL
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#define MC_VM_XGMI_LFB_CNTL_ALDE__PF_LFB_REGION__SHIFT 0x0
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#define MC_VM_XGMI_LFB_CNTL_ALDE__PF_MAX_REGION__SHIFT 0x4
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#define MC_VM_XGMI_LFB_CNTL_ALDE__PF_LFB_REGION_MASK 0x0000000FL
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#define MC_VM_XGMI_LFB_CNTL_ALDE__PF_MAX_REGION_MASK 0x000000F0L
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//MC_VM_XGMI_LFB_SIZE
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#define MC_VM_XGMI_LFB_SIZE_ALDE__PF_LFB_SIZE__SHIFT 0x0
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#define MC_VM_XGMI_LFB_SIZE_ALDE__PF_LFB_SIZE_MASK 0x0001FFFFL
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int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev)
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{
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u32 max_num_physical_nodes;
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u32 max_physical_node_id;
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u32 xgmi_lfb_cntl;
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u32 max_region;
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u64 seg_size;
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if (adev->asic_type == CHIP_ALDEBARAN) {
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xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL_ALDE);
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seg_size = REG_GET_FIELD(
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RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE_ALDE),
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MC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;
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max_region =
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REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL_ALDE, PF_MAX_REGION);
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} else {
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xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL);
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seg_size = REG_GET_FIELD(
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RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE),
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MC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;
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max_region =
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REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);
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}
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switch (adev->asic_type) {
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case CHIP_VEGA20:
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max_num_physical_nodes = 4;
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max_physical_node_id = 3;
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break;
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case CHIP_ARCTURUS:
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max_num_physical_nodes = 8;
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max_physical_node_id = 7;
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break;
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case CHIP_ALDEBARAN:
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max_num_physical_nodes = 16;
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max_physical_node_id = 15;
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break;
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default:
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return -EINVAL;
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}
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/* PF_MAX_REGION=0 means xgmi is disabled */
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if (max_region || adev->gmc.xgmi.connected_to_cpu) {
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adev->gmc.xgmi.num_physical_nodes = max_region + 1;
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if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes)
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return -EINVAL;
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if (adev->asic_type == CHIP_ALDEBARAN) {
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adev->gmc.xgmi.physical_node_id =
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REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL_ALDE,
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PF_LFB_REGION);
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} else {
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adev->gmc.xgmi.physical_node_id =
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REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL,
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PF_LFB_REGION);
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}
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if (adev->gmc.xgmi.physical_node_id > max_physical_node_id)
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return -EINVAL;
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adev->gmc.xgmi.node_segment_size = seg_size;
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}
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return 0;
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}
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