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RAS error address translation algorithm is common across dGPU and A + A platform as along as the SOC integrates the same generation of UMC IP. UMC RAS is managed by x86 MCA on A + A platform, umc_ras in GPU driver is not initialized at all on A + A platform. In such case, any umc_ras callback implemented for dGPU config shouldn't be invoked from A + A specific callback. The change moves convert_error_address out of dGPU umc_ras structure and makes it share between A + A and dGPU config. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Stanley Yang <Stanley.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
77 lines
3.4 KiB
C
77 lines
3.4 KiB
C
/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __UMC_V6_7_H__
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#define __UMC_V6_7_H__
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#include "soc15_common.h"
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#include "amdgpu.h"
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/* EccErrCnt max value */
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#define UMC_V6_7_CE_CNT_MAX 0xffff
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/* umc ce interrupt threshold */
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#define UMC_V6_7_CE_INT_THRESHOLD 0xffff
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/* umc ce count initial value */
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#define UMC_V6_7_CE_CNT_INIT (UMC_V6_7_CE_CNT_MAX - UMC_V6_7_CE_INT_THRESHOLD)
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#define UMC_V6_7_INST_DIST 0x40000
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/* number of umc channel instance with memory map register access */
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#define UMC_V6_7_UMC_INSTANCE_NUM 4
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/* number of umc instance with memory map register access */
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#define UMC_V6_7_CHANNEL_INSTANCE_NUM 8
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/* total channel instances in one umc block */
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#define UMC_V6_7_TOTAL_CHANNEL_NUM (UMC_V6_7_CHANNEL_INSTANCE_NUM * UMC_V6_7_UMC_INSTANCE_NUM)
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/* one piece of normalizing address is mapped to 8 pieces of physical address */
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#define UMC_V6_7_NA_MAP_PA_NUM 8
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/* R14 bit shift should be considered, double the number */
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#define UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL (UMC_V6_7_NA_MAP_PA_NUM * 2)
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/* The CH4 bit in SOC physical address */
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#define UMC_V6_7_PA_CH4_BIT 12
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/* The C2 bit in SOC physical address */
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#define UMC_V6_7_PA_C2_BIT 17
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/* The R14 bit in SOC physical address */
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#define UMC_V6_7_PA_R14_BIT 34
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/* UMC regiser per channel offset */
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#define UMC_V6_7_PER_CHANNEL_OFFSET 0x400
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/* XOR bit 20, 25, 34 of PA into CH4 bit (bit 12 of PA),
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* hash bit is only effective when related setting is enabled
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*/
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#define CHANNEL_HASH(channel_idx, pa) (((channel_idx) >> 4) ^ \
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(((pa) >> 20) & 0x1ULL & adev->df.hash_status.hash_64k) ^ \
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(((pa) >> 25) & 0x1ULL & adev->df.hash_status.hash_2m) ^ \
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(((pa) >> 34) & 0x1ULL & adev->df.hash_status.hash_1g))
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#define SET_CHANNEL_HASH(channel_idx, pa) do { \
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(pa) &= ~(0x1ULL << UMC_V6_7_PA_CH4_BIT); \
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(pa) |= (CHANNEL_HASH(channel_idx, pa) << UMC_V6_7_PA_CH4_BIT); \
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} while (0)
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extern struct amdgpu_umc_ras umc_v6_7_ras;
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extern const uint32_t
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umc_v6_7_channel_idx_tbl_second[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM];
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extern const uint32_t
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umc_v6_7_channel_idx_tbl_first[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM];
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void umc_v6_7_convert_error_address(struct amdgpu_device *adev,
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struct ras_err_data *err_data, uint64_t err_addr,
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uint32_t ch_inst, uint32_t umc_inst);
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#endif
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