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Introduces a driver for the LogiCVC display controller, a programmable logic controller optimized for use in Xilinx Zynq-7000 SoCs and other Xilinx FPGAs. The controller is mostly configured at logic synthesis time so only a subset of configuration is left for the driver to handle. The following features are implemented and tested: - LVDS 4-bit interface; - RGB565 pixel formats; - Multiple layers and hardware composition; - Layer-wide alpha mode; The following features are implemented but untested: - Other RGB pixel formats; - Layer framebuffer configuration for version 4; - Lowest-layer used as background color; - Per-pixel alpha mode. The following features are not implemented: - YUV pixel formats; - DVI, LVDS 3-bit, ITU656 and camera link interfaces; - External parallel input for layer; - Color-keying; - LUT-based alpha modes. Additional implementation-specific notes: - Panels are only enabled after the first page flip to avoid flashing a white screen. - Depth used in context of the LogiCVC driver only counts color components to match the definition of the synthesis parameters. Support is implemented for both version 3 and 4 of the controller. With version 3, framebuffers are stored in a dedicated contiguous memory area, with a base address hardcoded for each layer. This requires using a dedicated CMA pool registered at the base address and tweaking a few offset-related registers to try to use any buffer allocated from the pool. This is done on a best-effort basis to have the hardware cope with the DRM framebuffer allocation model and there is no guarantee that each buffer allocated by GEM CMA can be used for any layer. In particular, buffers allocated below the base address for a layer are guaranteed not to be configurable for that layer. See the implementation of logicvc_layer_buffer_find_setup for specifics. Version 4 allows configuring each buffer address directly, which guarantees that any buffer can be configured. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Reviewed-by: Maxime Ripard <mripard@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20220520141555.1429041-2-paul.kocialkowski@bootlin.com
80 lines
2.5 KiB
C
80 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2019-2022 Bootlin
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* Author: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
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*
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* Copyright (C) 2014 Xylon d.o.o.
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* Author: Davor Joja <davor.joja@logicbricks.com>
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*/
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#ifndef _LOGICVC_REGS_H_
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#define _LOGICVC_REGS_H_
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#define LOGICVC_DIMENSIONS_MAX (BIT(16) - 1)
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#define LOGICVC_HSYNC_FRONT_PORCH_REG 0x00
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#define LOGICVC_HSYNC_REG 0x08
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#define LOGICVC_HSYNC_BACK_PORCH_REG 0x10
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#define LOGICVC_HRES_REG 0x18
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#define LOGICVC_VSYNC_FRONT_PORCH_REG 0x20
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#define LOGICVC_VSYNC_REG 0x28
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#define LOGICVC_VSYNC_BACK_PORCH_REG 0x30
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#define LOGICVC_VRES_REG 0x38
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#define LOGICVC_CTRL_REG 0x40
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#define LOGICVC_CTRL_CLOCK_INVERT BIT(8)
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#define LOGICVC_CTRL_PIXEL_INVERT BIT(7)
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#define LOGICVC_CTRL_DE_INVERT BIT(5)
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#define LOGICVC_CTRL_DE_ENABLE BIT(4)
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#define LOGICVC_CTRL_VSYNC_INVERT BIT(3)
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#define LOGICVC_CTRL_VSYNC_ENABLE BIT(2)
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#define LOGICVC_CTRL_HSYNC_INVERT BIT(1)
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#define LOGICVC_CTRL_HSYNC_ENABLE BIT(0)
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#define LOGICVC_DTYPE_REG 0x48
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#define LOGICVC_BACKGROUND_COLOR_REG 0x50
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#define LOGICVC_BUFFER_SEL_REG 0x58
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#define LOGICVC_BUFFER_SEL_VALUE(i, v) \
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(BIT(10 + (i)) | ((v) << (2 * (i))))
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#define LOGICVC_BUFFER_SEL_MAX 2
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#define LOGICVC_DOUBLE_CLUT_REG 0x60
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#define LOGICVC_INT_STAT_REG 0x68
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#define LOGICVC_INT_STAT_V_SYNC BIT(5)
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#define LOGICVC_INT_MASK_REG 0x70
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#define LOGICVC_INT_MASK_V_SYNC BIT(5)
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#define LOGICVC_POWER_CTRL_REG 0x78
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#define LOGICVC_POWER_CTRL_BACKLIGHT_ENABLE BIT(0)
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#define LOGICVC_POWER_CTRL_VDD_ENABLE BIT(1)
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#define LOGICVC_POWER_CTRL_VEE_ENABLE BIT(2)
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#define LOGICVC_POWER_CTRL_VIDEO_ENABLE BIT(3)
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#define LOGICVC_IP_VERSION_REG 0xf8
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#define LOGICVC_IP_VERSION_MAJOR_MASK GENMASK(16, 11)
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#define LOGICVC_IP_VERSION_MINOR_MASK GENMASK(10, 5)
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#define LOGICVC_IP_VERSION_LEVEL_MASK GENMASK(4, 0)
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#define LOGICVC_LAYER_ADDRESS_REG(i) (0x100 + (i) * 0x80)
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#define LOGICVC_LAYER_HOFFSET_REG(i) (0x100 + (i) * 0x80)
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#define LOGICVC_LAYER_VOFFSET_REG(i) (0x108 + (i) * 0x80)
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#define LOGICVC_LAYER_VOFFSET_MAX 4095
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#define LOGICVC_LAYER_HPOSITION_REG(i) (0x110 + (i) * 0x80)
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#define LOGICVC_LAYER_VPOSITION_REG(i) (0x118 + (i) * 0x80)
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#define LOGICVC_LAYER_WIDTH_REG(i) (0x120 + (i) * 0x80)
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#define LOGICVC_LAYER_HEIGHT_REG(i) (0x128 + (i) * 0x80)
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#define LOGICVC_LAYER_ALPHA_REG(i) (0x130 + (i) * 0x80)
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#define LOGICVC_LAYER_CTRL_REG(i) (0x138 + (i) * 0x80)
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#define LOGICVC_LAYER_CTRL_ENABLE BIT(0)
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#define LOGICVC_LAYER_CTRL_COLOR_KEY_DISABLE BIT(1)
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#define LOGICVC_LAYER_CTRL_PIXEL_FORMAT_INVERT BIT(4)
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#define LOGICVC_LAYER_COLOR_KEY_REG(i) (0x140 + (i) * 0x80)
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#endif
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