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Bug 1673391 - Codegen test cases for binop-with-constant. r=jseward
Chiefly, we add many new test cases to binop-x64-ion-codegen.js to test that correct code is emitted for binop-with-constant. Secondarily, we simplify the codegen harness so that instructions that are split across two lines are handled automatically, it is not necessary to signify the line break explicitly using a \s at the end of the first line and a * at the beginning of the second. Thirdly, just clean up some formatting, and use RIPRADDR throughout in the binary disassembly. Differential Revision: https://phabricator.services.mozilla.com/D96004
This commit is contained in:
Lars T Hansen
parent
a555631f45
commit
c324814fd4
8 changed files with 262 additions and 52 deletions
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@ -10,12 +10,6 @@
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// replace any space string with \s+. Lines are separated by newlines and leading
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// and trailing spaces are currently stripped.
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//
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// Lines in expected-pattern starting with '*' are not prefixed by an address during
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// preprocessing.
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//
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// Lines in expected-pattern that end with a space (lines that are split do) must use \s
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// to represent that space.
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//
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// The testers additionally take an optional options bag with the following optional
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// entries:
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// no_prefix: if true, do not add a prefix string (normally the end of the prologue)
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@ -27,11 +21,15 @@
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var SPACEDEBUG = false;
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// Any hex string
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var HEXES = `[0-9a-fA-F]+`;
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var HEX = '[0-9a-fA-F]'
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var HEXES = `${HEX}+`;
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// RIP-relative address
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// RIP-relative address following the instruction mnemonic
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var RIPR = `0x${HEXES}`;
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// RIP-relative address in the binary encoding
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var RIPRADDR = `${HEX}{2} ${HEX}{2} ${HEX}{2} ${HEX}{2}`;
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// End of prologue
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var x64_prefix = `48 8b ec mov %rsp, %rbp`
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@ -67,6 +65,19 @@ function codegenTestX64_v128xLITERAL_v128(inputs, options = {}) {
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}
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}
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// literal OP v128 -> v128
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// inputs: [[complete-opname, lhs-literal, expected-pattern], ...]
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function codegenTestX64_LITERALxv128_v128(inputs, options = {}) {
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for ( let [op, literal, expected] of inputs ) {
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codegenTestX64_adhoc(wrap(options, `
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(func (export "f") (param v128) (result v128)
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(${op} ${literal} (local.get 0)))`),
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'f',
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expected,
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options)
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}
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}
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// v128 OP v128 -> v128, but operands are swapped
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// inputs: [[complete-opname, expected-pattern], ...]
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function codegenTestX64_v128xv128_v128_reversed(inputs, options = {}) {
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@ -169,7 +180,7 @@ function fixlines(s) {
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return s.split(/\n+/)
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.map(strip)
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.filter(x => x.length > 0)
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.map(x => x.charAt(0) == '*' ? x.substring(1) : (HEXES + ' ' + x))
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.map(x => HEXES + ' ' + x)
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.map(spaces)
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.join('\n');
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}
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@ -20,3 +20,220 @@ codegenTestX64_v128xv128_v128_reversed(
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['f32x4.pmax', `0f 5f c1 maxps %xmm1, %xmm0`],
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['f64x2.pmin', `66 0f 5d c1 minpd %xmm1, %xmm0`],
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['f64x2.pmax', `66 0f 5f c1 maxpd %xmm1, %xmm0`]] );
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// Constant arguments that are folded into the instruction
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codegenTestX64_v128xLITERAL_v128(
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[['i8x16.add', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f fc 05 ${RIPRADDR} paddbx ${RIPR}, %xmm0`],
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['i8x16.sub', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f f8 05 ${RIPRADDR} psubbx ${RIPR}, %xmm0`],
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['i8x16.add_sat_s', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f ec 05 ${RIPRADDR} paddsbx ${RIPR}, %xmm0`],
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['i8x16.add_sat_u', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f dc 05 ${RIPRADDR} paddusbx ${RIPR}, %xmm0`],
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['i8x16.sub_sat_s', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f e8 05 ${RIPRADDR} psubsbx ${RIPR}, %xmm0`],
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['i8x16.sub_sat_u', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f d8 05 ${RIPRADDR} psubusbx ${RIPR}, %xmm0`],
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['i8x16.min_s', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f 38 38 05 ${RIPRADDR} pminsbx ${RIPR}, %xmm0`],
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['i8x16.min_u', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f da 05 ${RIPRADDR} pminubx ${RIPR}, %xmm0`],
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['i8x16.max_s', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f 38 3c 05 ${RIPRADDR} pmaxsbx ${RIPR}, %xmm0`],
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['i8x16.max_u', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f de 05 ${RIPRADDR} pmaxubx ${RIPR}, %xmm0`],
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['i8x16.eq', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f 74 05 ${RIPRADDR} pcmpeqbx ${RIPR}, %xmm0`],
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['i8x16.ne', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)', `
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66 0f 74 05 ${RIPRADDR} pcmpeqbx ${RIPR}, %xmm0
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66 45 0f 75 ff pcmpeqw %xmm15, %xmm15
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66 41 0f ef c7 pxor %xmm15, %xmm0`],
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['i8x16.gt_s', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f 64 05 ${RIPRADDR} pcmpgtbx ${RIPR}, %xmm0`],
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['i8x16.le_s', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)', `
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66 0f 64 05 ${RIPRADDR} pcmpgtbx ${RIPR}, %xmm0
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66 45 0f 75 ff pcmpeqw %xmm15, %xmm15
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66 41 0f ef c7 pxor %xmm15, %xmm0`],
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['i8x16.narrow_i16x8_s', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f 63 05 ${RIPRADDR} packsswbx ${RIPR}, %xmm0`],
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['i8x16.narrow_i16x8_u', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f 67 05 ${RIPRADDR} packuswbx ${RIPR}, %xmm0`],
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['i16x8.add', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f fd 05 ${RIPRADDR} paddwx ${RIPR}, %xmm0`],
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['i16x8.sub', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f f9 05 ${RIPRADDR} psubwx ${RIPR}, %xmm0`],
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['i16x8.mul', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f d5 05 ${RIPRADDR} pmullwx ${RIPR}, %xmm0`],
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['i16x8.add_sat_s', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f ed 05 ${RIPRADDR} paddswx ${RIPR}, %xmm0`],
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['i16x8.add_sat_u', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f dd 05 ${RIPRADDR} padduswx ${RIPR}, %xmm0`],
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['i16x8.sub_sat_s', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f e9 05 ${RIPRADDR} psubswx ${RIPR}, %xmm0`],
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['i16x8.sub_sat_u', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f d9 05 ${RIPRADDR} psubuswx ${RIPR}, %xmm0`],
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['i16x8.min_s', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f ea 05 ${RIPRADDR} pminswx ${RIPR}, %xmm0`],
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['i16x8.min_u', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f 38 3a 05 ${RIPRADDR} pminuwx ${RIPR}, %xmm0`],
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['i16x8.max_s', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f ee 05 ${RIPRADDR} pmaxswx ${RIPR}, %xmm0`],
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['i16x8.max_u', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f 38 3e 05 ${RIPRADDR} pmaxuwx ${RIPR}, %xmm0`],
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['i16x8.eq', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f 75 05 ${RIPRADDR} pcmpeqwx ${RIPR}, %xmm0`],
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['i16x8.ne', '(v128.const i16x8 1 2 1 2 1 2 1 2)', `
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66 0f 75 05 ${RIPRADDR} pcmpeqwx ${RIPR}, %xmm0
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66 45 0f 75 ff pcmpeqw %xmm15, %xmm15
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66 41 0f ef c7 pxor %xmm15, %xmm0`],
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['i16x8.gt_s', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f 65 05 ${RIPRADDR} pcmpgtwx ${RIPR}, %xmm0`],
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['i16x8.le_s', '(v128.const i16x8 1 2 1 2 1 2 1 2)', `
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66 0f 65 05 ${RIPRADDR} pcmpgtwx ${RIPR}, %xmm0
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66 45 0f 75 ff pcmpeqw %xmm15, %xmm15
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66 41 0f ef c7 pxor %xmm15, %xmm0`],
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['i16x8.narrow_i32x4_s', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f 6b 05 ${RIPRADDR} packssdwx ${RIPR}, %xmm0`],
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['i16x8.narrow_i32x4_u', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f 38 2b 05 ${RIPRADDR} packusdwx ${RIPR}, %xmm0`],
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['i32x4.add', '(v128.const i32x4 1 2 1 2)',
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`66 0f fe 05 ${RIPRADDR} padddx ${RIPR}, %xmm0`],
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['i32x4.sub', '(v128.const i32x4 1 2 1 2)',
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`66 0f fa 05 ${RIPRADDR} psubdx ${RIPR}, %xmm0`],
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['i32x4.mul', '(v128.const i32x4 1 2 1 2)',
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`66 0f 38 40 05 ${RIPRADDR} pmulldx ${RIPR}, %xmm0`],
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['i32x4.min_s', '(v128.const i32x4 1 2 1 2)',
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`66 0f 38 39 05 ${RIPRADDR} pminsdx ${RIPR}, %xmm0`],
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['i32x4.min_u', '(v128.const i32x4 1 2 1 2)',
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`66 0f 38 3b 05 ${RIPRADDR} pminudx ${RIPR}, %xmm0`],
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['i32x4.max_s', '(v128.const i32x4 1 2 1 2)',
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`66 0f 38 3d 05 ${RIPRADDR} pmaxsdx ${RIPR}, %xmm0`],
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['i32x4.max_u', '(v128.const i32x4 1 2 1 2)',
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`66 0f 38 3f 05 ${RIPRADDR} pmaxudx ${RIPR}, %xmm0`],
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['i32x4.eq', '(v128.const i32x4 1 2 1 2)',
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`66 0f 76 05 ${RIPRADDR} pcmpeqdx ${RIPR}, %xmm0`],
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['i32x4.ne', '(v128.const i32x4 1 2 1 2)', `
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66 0f 76 05 ${RIPRADDR} pcmpeqdx ${RIPR}, %xmm0
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66 45 0f 75 ff pcmpeqw %xmm15, %xmm15
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66 41 0f ef c7 pxor %xmm15, %xmm0`],
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['i32x4.gt_s', '(v128.const i32x4 1 2 1 2)',
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`66 0f 66 05 ${RIPRADDR} pcmpgtdx ${RIPR}, %xmm0`],
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['i32x4.le_s', '(v128.const i32x4 1 2 1 2)', `
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66 0f 66 05 ${RIPRADDR} pcmpgtdx ${RIPR}, %xmm0
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66 45 0f 75 ff pcmpeqw %xmm15, %xmm15
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66 41 0f ef c7 pxor %xmm15, %xmm0`],
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['i32x4.dot_i16x8_s', '(v128.const i32x4 1 2 1 2)',
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`66 0f f5 05 ${RIPRADDR} pmaddwdx ${RIPR}, %xmm0`],
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['i64x2.add', '(v128.const i64x2 1 2)',
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`66 0f d4 05 ${RIPRADDR} paddqx ${RIPR}, %xmm0`],
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['i64x2.sub', '(v128.const i64x2 1 2)',
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`66 0f fb 05 ${RIPRADDR} psubqx ${RIPR}, %xmm0`],
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['v128.and', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f db 05 ${RIPRADDR} pandx ${RIPR}, %xmm0`],
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['v128.or', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f eb 05 ${RIPRADDR} porx ${RIPR}, %xmm0`],
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['v128.xor', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f ef 05 ${RIPRADDR} pxorx ${RIPR}, %xmm0`],
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['f32x4.add', '(v128.const f32x4 1 2 3 4)',
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`0f 58 05 ${RIPRADDR} addpsx ${RIPR}, %xmm0`],
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['f32x4.sub', '(v128.const f32x4 1 2 3 4)',
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`0f 5c 05 ${RIPRADDR} subpsx ${RIPR}, %xmm0`],
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['f32x4.mul', '(v128.const f32x4 1 2 3 4)',
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`0f 59 05 ${RIPRADDR} mulpsx ${RIPR}, %xmm0`],
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['f32x4.div', '(v128.const f32x4 1 2 3 4)',
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`0f 5e 05 ${RIPRADDR} divpsx ${RIPR}, %xmm0`],
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['f64x2.add', '(v128.const f64x2 1 2)',
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`66 0f 58 05 ${RIPRADDR} addpdx ${RIPR}, %xmm0`],
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['f64x2.sub', '(v128.const f64x2 1 2)',
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`66 0f 5c 05 ${RIPRADDR} subpdx ${RIPR}, %xmm0`],
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['f64x2.mul', '(v128.const f64x2 1 2)',
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`66 0f 59 05 ${RIPRADDR} mulpdx ${RIPR}, %xmm0`],
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['f64x2.div', '(v128.const f64x2 1 2)',
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`66 0f 5e 05 ${RIPRADDR} divpdx ${RIPR}, %xmm0`]]);
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// Commutative operations with constants on the lhs should generate the same
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// code as with the constant on the rhs.
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codegenTestX64_LITERALxv128_v128(
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[['i8x16.add', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f fc 05 ${RIPRADDR} paddbx ${RIPR}, %xmm0`],
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['i8x16.add_sat_s', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f ec 05 ${RIPRADDR} paddsbx ${RIPR}, %xmm0`],
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['i8x16.add_sat_u', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f dc 05 ${RIPRADDR} paddusbx ${RIPR}, %xmm0`],
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['i8x16.min_s', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f 38 38 05 ${RIPRADDR} pminsbx ${RIPR}, %xmm0`],
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['i8x16.min_u', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f da 05 ${RIPRADDR} pminubx ${RIPR}, %xmm0`],
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['i8x16.max_s', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f 38 3c 05 ${RIPRADDR} pmaxsbx ${RIPR}, %xmm0`],
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['i8x16.max_u', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f de 05 ${RIPRADDR} pmaxubx ${RIPR}, %xmm0`],
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['i8x16.eq', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
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`66 0f 74 05 ${RIPRADDR} pcmpeqbx ${RIPR}, %xmm0`],
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['i8x16.ne', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)', `
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66 0f 74 05 ${RIPRADDR} pcmpeqbx ${RIPR}, %xmm0
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66 45 0f 75 ff pcmpeqw %xmm15, %xmm15
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66 41 0f ef c7 pxor %xmm15, %xmm0`],
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['i16x8.add', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f fd 05 ${RIPRADDR} paddwx ${RIPR}, %xmm0`],
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['i16x8.mul', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f d5 05 ${RIPRADDR} pmullwx ${RIPR}, %xmm0`],
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['i16x8.add_sat_s', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f ed 05 ${RIPRADDR} paddswx ${RIPR}, %xmm0`],
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['i16x8.add_sat_u', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f dd 05 ${RIPRADDR} padduswx ${RIPR}, %xmm0`],
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['i16x8.min_s', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f ea 05 ${RIPRADDR} pminswx ${RIPR}, %xmm0`],
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['i16x8.min_u', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f 38 3a 05 ${RIPRADDR} pminuwx ${RIPR}, %xmm0`],
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['i16x8.max_s', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f ee 05 ${RIPRADDR} pmaxswx ${RIPR}, %xmm0`],
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['i16x8.max_u', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f 38 3e 05 ${RIPRADDR} pmaxuwx ${RIPR}, %xmm0`],
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['i16x8.eq', '(v128.const i16x8 1 2 1 2 1 2 1 2)',
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`66 0f 75 05 ${RIPRADDR} pcmpeqwx ${RIPR}, %xmm0`],
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['i16x8.ne', '(v128.const i16x8 1 2 1 2 1 2 1 2)', `
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66 0f 75 05 ${RIPRADDR} pcmpeqwx ${RIPR}, %xmm0
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66 45 0f 75 ff pcmpeqw %xmm15, %xmm15
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66 41 0f ef c7 pxor %xmm15, %xmm0`],
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['i32x4.add', '(v128.const i32x4 1 2 1 2)',
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`66 0f fe 05 ${RIPRADDR} padddx ${RIPR}, %xmm0`],
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['i32x4.mul', '(v128.const i32x4 1 2 1 2)',
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`66 0f 38 40 05 ${RIPRADDR} pmulldx ${RIPR}, %xmm0`],
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['i32x4.min_s', '(v128.const i32x4 1 2 1 2)',
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`66 0f 38 39 05 ${RIPRADDR} pminsdx ${RIPR}, %xmm0`],
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['i32x4.min_u', '(v128.const i32x4 1 2 1 2)',
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`66 0f 38 3b 05 ${RIPRADDR} pminudx ${RIPR}, %xmm0`],
|
||||
['i32x4.max_s', '(v128.const i32x4 1 2 1 2)',
|
||||
`66 0f 38 3d 05 ${RIPRADDR} pmaxsdx ${RIPR}, %xmm0`],
|
||||
['i32x4.max_u', '(v128.const i32x4 1 2 1 2)',
|
||||
`66 0f 38 3f 05 ${RIPRADDR} pmaxudx ${RIPR}, %xmm0`],
|
||||
['i32x4.eq', '(v128.const i32x4 1 2 1 2)',
|
||||
`66 0f 76 05 ${RIPRADDR} pcmpeqdx ${RIPR}, %xmm0`],
|
||||
['i32x4.ne', '(v128.const i32x4 1 2 1 2)', `
|
||||
66 0f 76 05 ${RIPRADDR} pcmpeqdx ${RIPR}, %xmm0
|
||||
66 45 0f 75 ff pcmpeqw %xmm15, %xmm15
|
||||
66 41 0f ef c7 pxor %xmm15, %xmm0`],
|
||||
['i32x4.dot_i16x8_s', '(v128.const i32x4 1 2 1 2)',
|
||||
`66 0f f5 05 ${RIPRADDR} pmaddwdx ${RIPR}, %xmm0`],
|
||||
|
||||
['i64x2.add', '(v128.const i64x2 1 2)',
|
||||
`66 0f d4 05 ${RIPRADDR} paddqx ${RIPR}, %xmm0`],
|
||||
|
||||
['v128.and', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
|
||||
`66 0f db 05 ${RIPRADDR} pandx ${RIPR}, %xmm0`],
|
||||
['v128.or', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
|
||||
`66 0f eb 05 ${RIPRADDR} porx ${RIPR}, %xmm0`],
|
||||
['v128.xor', '(v128.const i8x16 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2)',
|
||||
`66 0f ef 05 ${RIPRADDR} pxorx ${RIPR}, %xmm0`]]);
|
||||
|
|
|
|||
|
|
@ -58,19 +58,16 @@ codegenTestX64_v128xv128_v128_reversed(
|
|||
[['i8x16.ge_s', `
|
||||
66 0f 64 c1 pcmpgtb %xmm1, %xmm0
|
||||
66 45 0f 75 ff pcmpeqw %xmm15, %xmm15
|
||||
66 41 0f ef c7 pxor %xmm15, %xmm0
|
||||
`],
|
||||
66 41 0f ef c7 pxor %xmm15, %xmm0`],
|
||||
['i16x8.ge_s',
|
||||
`
|
||||
66 0f 65 c1 pcmpgtw %xmm1, %xmm0
|
||||
66 45 0f 75 ff pcmpeqw %xmm15, %xmm15
|
||||
66 41 0f ef c7 pxor %xmm15, %xmm0
|
||||
`],
|
||||
66 41 0f ef c7 pxor %xmm15, %xmm0`],
|
||||
['i32x4.ge_s', `
|
||||
66 0f 66 c1 pcmpgtd %xmm1, %xmm0
|
||||
66 45 0f 75 ff pcmpeqw %xmm15, %xmm15
|
||||
66 41 0f ef c7 pxor %xmm15, %xmm0
|
||||
`],
|
||||
66 41 0f ef c7 pxor %xmm15, %xmm0`],
|
||||
['i8x16.lt_s', `66 0f 64 c1 pcmpgtb %xmm1, %xmm0`],
|
||||
['i16x8.lt_s', `66 0f 65 c1 pcmpgtw %xmm1, %xmm0`],
|
||||
['i32x4.lt_s', `66 0f 66 c1 pcmpgtd %xmm1, %xmm0`],
|
||||
|
|
|
|||
|
|
@ -13,18 +13,15 @@ codegenTestX64_v128_v128(
|
|||
`
|
||||
44 0f 28 f8 movaps %xmm0, %xmm15
|
||||
45 0f c2 ff 00 cmpps \\$0x00, %xmm15, %xmm15
|
||||
66 41 0f db c7 pand %xmm15, %xmm0
|
||||
`],
|
||||
66 41 0f db c7 pand %xmm15, %xmm0`],
|
||||
['i32x4.trunc_sat_f32x4_u', `
|
||||
66 45 0f ef ff pxor %xmm15, %xmm15
|
||||
41 0f 5f c7 maxps %xmm15, %xmm0
|
||||
`],
|
||||
41 0f 5f c7 maxps %xmm15, %xmm0`],
|
||||
['f32x4.convert_i32x4_u', `
|
||||
66 45 0f ef ff pxor %xmm15, %xmm15
|
||||
66 44 0f 3a 0e f8 55 pblendw \\$0x55, %xmm0, %xmm15
|
||||
66 41 0f fa c7 psubd %xmm15, %xmm0
|
||||
45 0f 5b ff cvtdq2ps %xmm15, %xmm15
|
||||
`]],
|
||||
45 0f 5b ff cvtdq2ps %xmm15, %xmm15`]],
|
||||
{no_suffix:true});
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -10,30 +10,25 @@
|
|||
codegenTestX64_IGNOREDxv128_v128(
|
||||
[['i8x16.neg', `
|
||||
66 0f ef c0 pxor %xmm0, %xmm0
|
||||
66 0f f8 c1 psubb %xmm1, %xmm0
|
||||
`],
|
||||
66 0f f8 c1 psubb %xmm1, %xmm0`],
|
||||
['i16x8.neg', `
|
||||
66 0f ef c0 pxor %xmm0, %xmm0
|
||||
66 0f f9 c1 psubw %xmm1, %xmm0
|
||||
`],
|
||||
66 0f f9 c1 psubw %xmm1, %xmm0`],
|
||||
['i32x4.neg', `
|
||||
66 0f ef c0 pxor %xmm0, %xmm0
|
||||
66 0f fa c1 psubd %xmm1, %xmm0
|
||||
`],
|
||||
66 0f fa c1 psubd %xmm1, %xmm0`],
|
||||
['i64x2.neg', `
|
||||
66 0f ef c0 pxor %xmm0, %xmm0
|
||||
66 0f fb c1 psubq %xmm1, %xmm0
|
||||
`]] );
|
||||
66 0f fb c1 psubq %xmm1, %xmm0`]] );
|
||||
|
||||
// Floating point negate and absolute value, and bitwise not, prefer for the
|
||||
// registers to be the same and guarantee that no move is inserted if so.
|
||||
|
||||
codegenTestX64_v128_v128(
|
||||
[['f32x4.neg', `66 0f ef 05 .. 00 00 00 pxorx ${RIPR}, %xmm0`],
|
||||
['f64x2.neg', `66 0f ef 05 .. 00 00 00 pxorx ${RIPR}, %xmm0`],
|
||||
['f32x4.abs', `66 0f db 05 .. 00 00 00 pandx ${RIPR}, %xmm0`],
|
||||
['f64x2.abs', `66 0f db 05 .. 00 00 00 pandx ${RIPR}, %xmm0`],
|
||||
[['f32x4.neg', `66 0f ef 05 ${RIPRADDR} pxorx ${RIPR}, %xmm0`],
|
||||
['f64x2.neg', `66 0f ef 05 ${RIPRADDR} pxorx ${RIPR}, %xmm0`],
|
||||
['f32x4.abs', `66 0f db 05 ${RIPRADDR} pandx ${RIPR}, %xmm0`],
|
||||
['f64x2.abs', `66 0f db 05 ${RIPRADDR} pandx ${RIPR}, %xmm0`],
|
||||
['v128.not', `
|
||||
66 45 0f 75 ff pcmpeqw %xmm15, %xmm15
|
||||
66 41 0f ef c7 pxor %xmm15, %xmm0
|
||||
`]] );
|
||||
66 41 0f ef c7 pxor %xmm15, %xmm0`]] );
|
||||
|
|
|
|||
|
|
@ -10,15 +10,13 @@
|
|||
codegenTestX64_v128xLITERAL_v128(
|
||||
[['i8x16.shl', '(i32.const 2)', `
|
||||
66 0f fc c0 paddb %xmm0, %xmm0
|
||||
66 0f fc c0 paddb %xmm0, %xmm0
|
||||
`],
|
||||
66 0f fc c0 paddb %xmm0, %xmm0`],
|
||||
['i16x8.shl', '(i32.const 2)', `66 0f 71 f0 02 psllw \\$0x02, %xmm0`],
|
||||
['i32x4.shl', '(i32.const 2)', `66 0f 72 f0 02 pslld \\$0x02, %xmm0`],
|
||||
['i64x2.shl', '(i32.const 2)', `66 0f 73 f0 02 psllq \\$0x02, %xmm0`],
|
||||
['i8x16.shr_u', '(i32.const 2)', `
|
||||
66 0f db 05 .. 00 00 00 pandx ${RIPR}, %xmm0
|
||||
66 0f 71 d0 02 psrlw \\$0x02, %xmm0
|
||||
`],
|
||||
66 0f db 05 ${RIPRADDR} pandx ${RIPR}, %xmm0
|
||||
66 0f 71 d0 02 psrlw \\$0x02, %xmm0`],
|
||||
['i16x8.shr_s', '(i32.const 2)', `66 0f 71 e0 02 psraw \\$0x02, %xmm0`],
|
||||
['i16x8.shr_u', '(i32.const 2)', `66 0f 71 d0 02 psrlw \\$0x02, %xmm0`],
|
||||
['i32x4.shr_s', '(i32.const 2)', `66 0f 72 e0 02 psrad \\$0x02, %xmm0`],
|
||||
|
|
|
|||
|
|
@ -29,9 +29,8 @@ f2 0f 70 c0 aa pshuflw \\$0xAA, %xmm0, %xmm0
|
|||
// Permute bytes
|
||||
['i8x16.shuffle 2 1 4 3 6 5 8 7 10 9 12 11 14 13 0 15',
|
||||
`
|
||||
66 44 0f 6f 3d .. 00 00 00\\s
|
||||
* movdqax ${RIPR}, %xmm15
|
||||
66 41 0f 38 00 c7 pshufb %xmm15, %xmm0`],
|
||||
66 44 0f 6f 3d ${RIPRADDR} movdqax ${RIPR}, %xmm15
|
||||
66 41 0f 38 00 c7 pshufb %xmm15, %xmm0`],
|
||||
|
||||
// Permute words
|
||||
['i8x16.shuffle 2 3 0 1 6 7 4 5 10 11 8 9 14 15 12 13',
|
||||
|
|
@ -51,13 +50,10 @@ f3 0f 70 c0 b1 pshufhw \\$0xB1, %xmm0, %xmm0`],
|
|||
// unless we can convince the compiler that it's OK to destroy xmm1.
|
||||
['i8x16.shuffle 15 29 0 1 2 1 2 0 3 4 7 8 16 8 17 9',
|
||||
`
|
||||
66 44 0f 6f f9 movdqa %xmm1, %xmm15
|
||||
66 44 0f 38 00 3d .. 00 00 00\\s
|
||||
* pshufbx ${RIPR}, %xmm15
|
||||
66 0f 38 00 05 .. 00 00 00\\s
|
||||
* pshufbx ${RIPR}, %xmm0
|
||||
66 41 0f eb c7 por %xmm15, %xmm0`],
|
||||
]);
|
||||
66 44 0f 6f f9 movdqa %xmm1, %xmm15
|
||||
66 44 0f 38 00 3d ${RIPRADDR} pshufbx ${RIPR}, %xmm15
|
||||
66 0f 38 00 05 ${RIPRADDR} pshufbx ${RIPR}, %xmm0
|
||||
66 41 0f eb c7 por %xmm15, %xmm0`]]);
|
||||
|
||||
codegenTestX64_v128xLITERAL_v128(
|
||||
[// Shift left bytes, shifting in zeroes
|
||||
|
|
|
|||
|
|
@ -17,8 +17,7 @@ if (!getBuildConfiguration().windows) {
|
|||
codegenTestX64_PTYPE_v128(
|
||||
[['v128.load32_splat', 'i32', `
|
||||
f3 41 0f 10 04 3f movssl \\(%r15,%rdi,1\\), %xmm0
|
||||
0f c6 c0 00 shufps \\$0x00, %xmm0, %xmm0
|
||||
`],
|
||||
0f c6 c0 00 shufps \\$0x00, %xmm0, %xmm0`],
|
||||
['v128.load64_splat', 'i32', `f2 41 0f 12 04 3f movddupq \\(%r15,%rdi,1\\), %xmm0`],
|
||||
['v128.load8x8_s', 'i32', `66 41 0f 38 20 04 3f pmovsxbwq \\(%r15,%rdi,1\\), %xmm0`],
|
||||
['v128.load8x8_u', 'i32', `66 41 0f 38 30 04 3f pmovzxbwq \\(%r15,%rdi,1\\), %xmm0`],
|
||||
|
|
|
|||
Loading…
Reference in a new issue