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Bug 1823857 - part 2: arm64 simulator: inline a couple of small routines that are hot. r=rhunt.

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The routines are used for loads and stores, so this minor improvement is
widely applicable.  Reduces (host) instruction count by around 2% for
wasm-baseline generated arm64 code.

Depends on D173275

Differential Revision: https://phabricator.services.mozilla.com/D173276
This commit is contained in:
Julian Seward 2023-03-22 13:17:58 +00:00
parent 821290a1e3
commit ebb16c58db
3 changed files with 16 additions and 19 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

15
js/src/jit/arm64/vixl/Instructions-vixl.cpp
View file

@ -206,21 +206,6 @@ double Instruction::ImmNEONFP64() const {
return Imm8ToFP64(ImmNEONabcdefgh()); return Imm8ToFP64(ImmNEONabcdefgh());
} }
unsigned CalcLSDataSize(LoadStoreOp op) {
VIXL_ASSERT((LSSize_offset + LSSize_width) == (kInstructionSize * 8));
unsigned size = static_cast<Instr>(op) >> LSSize_offset;
if ((op & LSVector_mask) != 0) {
// Vector register memory operations encode the access size in the "size"
// and "opc" fields.
if ((size == 0) && ((op & LSOpc_mask) >> LSOpc_offset) >= 2) {
size = kQRegSizeInBytesLog2;
}
}
return size;
}
unsigned CalcLSPairDataSize(LoadStorePairOp op) { unsigned CalcLSPairDataSize(LoadStorePairOp op) {
VIXL_STATIC_ASSERT(kXRegSizeInBytes == kDRegSizeInBytes); VIXL_STATIC_ASSERT(kXRegSizeInBytes == kDRegSizeInBytes);
VIXL_STATIC_ASSERT(kWRegSizeInBytes == kSRegSizeInBytes); VIXL_STATIC_ASSERT(kWRegSizeInBytes == kSRegSizeInBytes);

14
js/src/jit/arm64/vixl/Instructions-vixl.h
View file

@ -104,7 +104,19 @@ const uint64_t kAddressTagMask =
((UINT64_C(1) << kAddressTagWidth) - 1) << kAddressTagOffset; ((UINT64_C(1) << kAddressTagWidth) - 1) << kAddressTagOffset;
VIXL_STATIC_ASSERT(kAddressTagMask == UINT64_C(0xff00000000000000)); VIXL_STATIC_ASSERT(kAddressTagMask == UINT64_C(0xff00000000000000));
unsigned CalcLSDataSize(LoadStoreOp op); static inline unsigned CalcLSDataSize(LoadStoreOp op) {
VIXL_ASSERT((LSSize_offset + LSSize_width) == (kInstructionSize * 8));
unsigned size = static_cast<Instr>(op) >> LSSize_offset;
if ((op & LSVector_mask) != 0) {
// Vector register memory operations encode the access size in the "size"
// and "opc" fields.
if ((size == 0) && ((op & LSOpc_mask) >> LSOpc_offset) >= 2) {
size = kQRegSizeInBytesLog2;
}
}
return size;
}
unsigned CalcLSPairDataSize(LoadStorePairOp op); unsigned CalcLSPairDataSize(LoadStorePairOp op);
enum ImmBranchType { enum ImmBranchType {

6
js/src/jit/arm64/vixl/Simulator-vixl.h
View file

@ -988,13 +988,13 @@ class Simulator : public DecoderVisitor {
void PrintWrittenVRegisters(); void PrintWrittenVRegisters();
// As above, but respect LOG_REG and LOG_VREG. // As above, but respect LOG_REG and LOG_VREG.
void LogWrittenRegisters() { inline void LogWrittenRegisters() {
if (trace_parameters() & LOG_REGS) PrintWrittenRegisters(); if (trace_parameters() & LOG_REGS) PrintWrittenRegisters();
} }
void LogWrittenVRegisters() { inline void LogWrittenVRegisters() {
if (trace_parameters() & LOG_VREGS) PrintWrittenVRegisters(); if (trace_parameters() & LOG_VREGS) PrintWrittenVRegisters();
} }
void LogAllWrittenRegisters() { inline void LogAllWrittenRegisters() {
LogWrittenRegisters(); LogWrittenRegisters();
LogWrittenVRegisters(); LogWrittenVRegisters();
} }