forked from mirrors/linux
[POWERPC] Cell "Spider" MMIO workarounds
This patch implements a workaround for a Spider PCI host bridge bug where it doesn't enforce some of the PCI ordering rules unless some manual manipulation of a special register is done. In order to be fully compliant with the PCI spec, I do this on every MMIO read operation. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Benjamin Herrenschmidt
Paul Mackerras
parent
4cb3cee03d
commit
014da7ff47
3 changed files with 349 additions and 2 deletions
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@ -476,6 +476,7 @@ config PPC_CELL_NATIVE
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select PPC_CELL
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select PPC_DCR_MMIO
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select PPC_OF_PLATFORM_PCI
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select PPC_INDIRECT_IO
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select MPIC
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default n
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@ -1,6 +1,6 @@
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obj-$(CONFIG_PPC_CELL_NATIVE) += interrupt.o iommu.o setup.o \
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cbe_regs.o spider-pic.o pervasive.o \
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pmu.o
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cbe_regs.o spider-pic.o \
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pervasive.o pmu.o io-workarounds.o
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obj-$(CONFIG_CBE_RAS) += ras.o
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obj-$(CONFIG_CBE_THERM) += cbe_thermal.o
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346
arch/powerpc/platforms/cell/io-workarounds.c
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346
arch/powerpc/platforms/cell/io-workarounds.c
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@ -0,0 +1,346 @@
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/*
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* Copyright (C) 2006 Benjamin Herrenschmidt <benh@kernel.crashing.org>
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* IBM, Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/pci.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/ppc-pci.h>
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#define SPIDER_PCI_REG_BASE 0xd000
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#define SPIDER_PCI_VCI_CNTL_STAT 0x0110
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#define SPIDER_PCI_DUMMY_READ 0x0810
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#define SPIDER_PCI_DUMMY_READ_BASE 0x0814
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/* Undefine that to re-enable bogus prefetch
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*
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* Without that workaround, the chip will do bogus prefetch past
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* page boundary from system memory. This setting will disable that,
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* though the documentation is unclear as to the consequences of doing
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* so, either purely performances, or possible misbehaviour... It's not
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* clear wether the chip can handle unaligned accesses at all without
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* prefetching enabled.
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*
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* For now, things appear to be behaving properly with that prefetching
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* disabled and IDE, possibly because IDE isn't doing any unaligned
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* access.
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*/
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#define SPIDER_DISABLE_PREFETCH
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#define MAX_SPIDERS 2
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static struct spider_pci_bus {
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void __iomem *regs;
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unsigned long mmio_start;
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unsigned long mmio_end;
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unsigned long pio_vstart;
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unsigned long pio_vend;
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} spider_pci_busses[MAX_SPIDERS];
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static int spider_pci_count;
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static struct spider_pci_bus *spider_pci_find(unsigned long vaddr,
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unsigned long paddr)
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{
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int i;
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for (i = 0; i < spider_pci_count; i++) {
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struct spider_pci_bus *bus = &spider_pci_busses[i];
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if (paddr && paddr >= bus->mmio_start && paddr < bus->mmio_end)
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return bus;
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if (vaddr && vaddr >= bus->pio_vstart && vaddr < bus->pio_vend)
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return bus;
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}
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return NULL;
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}
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static void spider_io_flush(const volatile void __iomem *addr)
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{
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struct spider_pci_bus *bus;
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int token;
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/* Get platform token (set by ioremap) from address */
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token = PCI_GET_ADDR_TOKEN(addr);
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/* Fast path if we have a non-0 token, it indicates which bus we
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* are on.
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*
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* If the token is 0, that means either the the ioremap was done
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* before we initialized this layer, or it's a PIO operation. We
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* fallback to a low path in this case. Hopefully, internal devices
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* which are ioremap'ed early should use in_XX/out_XX functions
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* instead of the PCI ones and thus not suffer from the slowdown.
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*
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* Also note that currently, the workaround will not work for areas
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* that are not mapped with PTEs (bolted in the hash table). This
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* is the case for ioremaps done very early at boot (before
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* mem_init_done) and includes the mapping of the ISA IO space.
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*
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* Fortunately, none of the affected devices is expected to do DMA
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* and thus there should be no problem in practice.
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*
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* In order to improve performances, we only do the PTE search for
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* addresses falling in the PHB IO space area. That means it will
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* not work for hotplug'ed PHBs but those don't exist with Spider.
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*/
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if (token && token <= spider_pci_count)
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bus = &spider_pci_busses[token - 1];
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else {
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unsigned long vaddr, paddr;
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pte_t *ptep;
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/* Fixup physical address */
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vaddr = (unsigned long)PCI_FIX_ADDR(addr);
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/* Check if it's in allowed range for PIO */
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if (vaddr < PHBS_IO_BASE || vaddr >= IMALLOC_BASE)
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return;
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/* Try to find a PTE. If not, clear the paddr, we'll do
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* a vaddr only lookup (PIO only)
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*/
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ptep = find_linux_pte(init_mm.pgd, vaddr);
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if (ptep == NULL)
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paddr = 0;
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else
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paddr = pte_pfn(*ptep) << PAGE_SHIFT;
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bus = spider_pci_find(vaddr, paddr);
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if (bus == NULL)
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return;
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}
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/* Now do the workaround
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*/
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(void)in_be32(bus->regs + SPIDER_PCI_DUMMY_READ);
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}
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static u8 spider_readb(const volatile void __iomem *addr)
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{
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u8 val = __do_readb(addr);
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spider_io_flush(addr);
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return val;
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}
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static u16 spider_readw(const volatile void __iomem *addr)
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{
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u16 val = __do_readw(addr);
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spider_io_flush(addr);
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return val;
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}
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static u32 spider_readl(const volatile void __iomem *addr)
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{
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u32 val = __do_readl(addr);
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spider_io_flush(addr);
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return val;
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}
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static u64 spider_readq(const volatile void __iomem *addr)
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{
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u64 val = __do_readq(addr);
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spider_io_flush(addr);
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return val;
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}
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static u16 spider_readw_be(const volatile void __iomem *addr)
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{
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u16 val = __do_readw_be(addr);
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spider_io_flush(addr);
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return val;
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}
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static u32 spider_readl_be(const volatile void __iomem *addr)
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{
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u32 val = __do_readl_be(addr);
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spider_io_flush(addr);
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return val;
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}
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static u64 spider_readq_be(const volatile void __iomem *addr)
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{
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u64 val = __do_readq_be(addr);
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spider_io_flush(addr);
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return val;
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}
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static void spider_readsb(const volatile void __iomem *addr, void *buf,
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unsigned long count)
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{
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__do_readsb(addr, buf, count);
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spider_io_flush(addr);
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}
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static void spider_readsw(const volatile void __iomem *addr, void *buf,
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unsigned long count)
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{
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__do_readsw(addr, buf, count);
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spider_io_flush(addr);
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}
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static void spider_readsl(const volatile void __iomem *addr, void *buf,
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unsigned long count)
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{
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__do_readsl(addr, buf, count);
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spider_io_flush(addr);
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}
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static void spider_memcpy_fromio(void *dest, const volatile void __iomem *src,
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unsigned long n)
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{
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__do_memcpy_fromio(dest, src, n);
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spider_io_flush(src);
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}
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static void __iomem * spider_ioremap(unsigned long addr, unsigned long size,
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unsigned long flags)
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{
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struct spider_pci_bus *bus;
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void __iomem *res = __ioremap(addr, size, flags);
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int busno;
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pr_debug("spider_ioremap(0x%lx, 0x%lx, 0x%lx) -> 0x%p\n",
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addr, size, flags, res);
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bus = spider_pci_find(0, addr);
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if (bus != NULL) {
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busno = bus - spider_pci_busses;
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pr_debug(" found bus %d, setting token\n", busno);
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PCI_SET_ADDR_TOKEN(res, busno + 1);
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}
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pr_debug(" result=0x%p\n", res);
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return res;
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}
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static void __init spider_pci_setup_chip(struct spider_pci_bus *bus)
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{
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#ifdef SPIDER_DISABLE_PREFETCH
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u32 val = in_be32(bus->regs + SPIDER_PCI_VCI_CNTL_STAT);
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pr_debug(" PVCI_Control_Status was 0x%08x\n", val);
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out_be32(bus->regs + SPIDER_PCI_VCI_CNTL_STAT, val | 0x8);
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#endif
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/* Configure the dummy address for the workaround */
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out_be32(bus->regs + SPIDER_PCI_DUMMY_READ_BASE, 0x80000000);
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}
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static void __init spider_pci_add_one(struct pci_controller *phb)
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{
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struct spider_pci_bus *bus = &spider_pci_busses[spider_pci_count];
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struct device_node *np = phb->arch_data;
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struct resource rsrc;
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void __iomem *regs;
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if (spider_pci_count >= MAX_SPIDERS) {
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printk(KERN_ERR "Too many spider bridges, workarounds"
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" disabled for %s\n", np->full_name);
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return;
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}
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/* Get the registers for the beast */
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if (of_address_to_resource(np, 0, &rsrc)) {
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printk(KERN_ERR "Failed to get registers for spider %s"
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" workarounds disabled\n", np->full_name);
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return;
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}
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/* Mask out some useless bits in there to get to the base of the
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* spider chip
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*/
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rsrc.start &= ~0xfffffffful;
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/* Map them */
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regs = ioremap(rsrc.start + SPIDER_PCI_REG_BASE, 0x1000);
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if (regs == NULL) {
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printk(KERN_ERR "Failed to map registers for spider %s"
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" workarounds disabled\n", np->full_name);
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return;
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}
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spider_pci_count++;
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/* We assume spiders only have one MMIO resource */
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bus->mmio_start = phb->mem_resources[0].start;
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bus->mmio_end = phb->mem_resources[0].end + 1;
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bus->pio_vstart = (unsigned long)phb->io_base_virt;
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bus->pio_vend = bus->pio_vstart + phb->pci_io_size;
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bus->regs = regs;
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printk(KERN_INFO "PCI: Spider MMIO workaround for %s\n",np->full_name);
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pr_debug(" mmio (P) = 0x%016lx..0x%016lx\n",
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bus->mmio_start, bus->mmio_end);
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pr_debug(" pio (V) = 0x%016lx..0x%016lx\n",
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bus->pio_vstart, bus->pio_vend);
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pr_debug(" regs (P) = 0x%016lx (V) = 0x%p\n",
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rsrc.start + SPIDER_PCI_REG_BASE, bus->regs);
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spider_pci_setup_chip(bus);
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}
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static struct ppc_pci_io __initdata spider_pci_io = {
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.readb = spider_readb,
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.readw = spider_readw,
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.readl = spider_readl,
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.readq = spider_readq,
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.readw_be = spider_readw_be,
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.readl_be = spider_readl_be,
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.readq_be = spider_readq_be,
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.readsb = spider_readsb,
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.readsw = spider_readsw,
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.readsl = spider_readsl,
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.memcpy_fromio = spider_memcpy_fromio,
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};
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static int __init spider_pci_workaround_init(void)
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{
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struct pci_controller *phb;
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if (!machine_is(cell))
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return 0;
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/* Find spider bridges. We assume they have been all probed
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* in setup_arch(). If that was to change, we would need to
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* update this code to cope with dynamically added busses
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*/
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list_for_each_entry(phb, &hose_list, list_node) {
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struct device_node *np = phb->arch_data;
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const char *model = get_property(np, "model", NULL);
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/* If no model property or name isn't exactly "pci", skip */
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if (model == NULL || strcmp(np->name, "pci"))
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continue;
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/* If model is not "Spider", skip */
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if (strcmp(model, "Spider"))
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continue;
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spider_pci_add_one(phb);
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}
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/* No Spider PCI found, exit */
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if (spider_pci_count == 0)
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return 0;
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/* Setup IO callbacks. We only setup MMIO reads. PIO reads will
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* fallback to MMIO reads (though without a token, thus slower)
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*/
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ppc_pci_io = spider_pci_io;
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/* Setup ioremap callback */
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ppc_md.ioremap = spider_ioremap;
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return 0;
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}
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arch_initcall(spider_pci_workaround_init);
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