forked from mirrors/linux
iommu/mediatek: Add mt8173 IOMMU driver
This patch adds support for mediatek m4u (MultiMedia Memory Management Unit). Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Yong Wu
Joerg Roedel
parent
cc8bbe1a83
commit
0df4fabe20
3 changed files with 754 additions and 0 deletions
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@ -337,4 +337,20 @@ config S390_IOMMU
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help
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Support for the IOMMU API for s390 PCI devices.
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config MTK_IOMMU
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bool "MTK IOMMU Support"
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depends on ARM || ARM64
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depends on ARCH_MEDIATEK || COMPILE_TEST
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select IOMMU_API
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select IOMMU_DMA
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select IOMMU_IO_PGTABLE_ARMV7S
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select MEMORY
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select MTK_SMI
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help
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Support for the M4U on certain Mediatek SOCs. M4U is MultiMedia
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Memory Management Unit. This option enables remapping of DMA memory
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accesses for the multimedia subsystem.
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If unsure, say N here.
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endif # IOMMU_SUPPORT
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@ -17,6 +17,7 @@ obj-$(CONFIG_INTEL_IOMMU) += intel-iommu.o
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obj-$(CONFIG_INTEL_IOMMU_SVM) += intel-svm.o
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obj-$(CONFIG_IPMMU_VMSA) += ipmmu-vmsa.o
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obj-$(CONFIG_IRQ_REMAP) += intel_irq_remapping.o irq_remapping.o
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obj-$(CONFIG_MTK_IOMMU) += mtk_iommu.o
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obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o
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obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o
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obj-$(CONFIG_ROCKCHIP_IOMMU) += rockchip-iommu.o
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737
drivers/iommu/mtk_iommu.c
Normal file
737
drivers/iommu/mtk_iommu.c
Normal file
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@ -0,0 +1,737 @@
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/*
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* Copyright (c) 2015-2016 MediaTek Inc.
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* Author: Yong Wu <yong.wu@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/bug.h>
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/device.h>
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#include <linux/dma-iommu.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iommu.h>
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#include <linux/iopoll.h>
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#include <linux/list.h>
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#include <linux/of_address.h>
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#include <linux/of_iommu.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <asm/barrier.h>
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#include <dt-bindings/memory/mt8173-larb-port.h>
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#include <soc/mediatek/smi.h>
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#include "io-pgtable.h"
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#define REG_MMU_PT_BASE_ADDR 0x000
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#define REG_MMU_INVALIDATE 0x020
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#define F_ALL_INVLD 0x2
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#define F_MMU_INV_RANGE 0x1
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#define REG_MMU_INVLD_START_A 0x024
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#define REG_MMU_INVLD_END_A 0x028
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#define REG_MMU_INV_SEL 0x038
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#define F_INVLD_EN0 BIT(0)
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#define F_INVLD_EN1 BIT(1)
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#define REG_MMU_STANDARD_AXI_MODE 0x048
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#define REG_MMU_DCM_DIS 0x050
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#define REG_MMU_CTRL_REG 0x110
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#define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4)
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#define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5)
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#define REG_MMU_IVRP_PADDR 0x114
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#define F_MMU_IVRP_PA_SET(pa) ((pa) >> 1)
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#define REG_MMU_INT_CONTROL0 0x120
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#define F_L2_MULIT_HIT_EN BIT(0)
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#define F_TABLE_WALK_FAULT_INT_EN BIT(1)
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#define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2)
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#define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3)
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#define F_PREFETCH_FIFO_ERR_INT_EN BIT(5)
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#define F_MISS_FIFO_ERR_INT_EN BIT(6)
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#define F_INT_CLR_BIT BIT(12)
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#define REG_MMU_INT_MAIN_CONTROL 0x124
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#define F_INT_TRANSLATION_FAULT BIT(0)
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#define F_INT_MAIN_MULTI_HIT_FAULT BIT(1)
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#define F_INT_INVALID_PA_FAULT BIT(2)
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#define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3)
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#define F_INT_TLB_MISS_FAULT BIT(4)
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#define F_INT_MISS_TRANSACTION_FIFO_FAULT BIT(5)
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#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT BIT(6)
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#define REG_MMU_CPE_DONE 0x12C
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#define REG_MMU_FAULT_ST1 0x134
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#define REG_MMU_FAULT_VA 0x13c
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#define F_MMU_FAULT_VA_MSK 0xfffff000
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#define F_MMU_FAULT_VA_WRITE_BIT BIT(1)
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#define F_MMU_FAULT_VA_LAYER_BIT BIT(0)
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#define REG_MMU_INVLD_PA 0x140
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#define REG_MMU_INT_ID 0x150
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#define F_MMU0_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
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#define F_MMU0_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
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#define MTK_PROTECT_PA_ALIGN 128
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struct mtk_iommu_suspend_reg {
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u32 standard_axi_mode;
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u32 dcm_dis;
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u32 ctrl_reg;
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u32 int_control0;
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u32 int_main_control;
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};
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struct mtk_iommu_client_priv {
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struct list_head client;
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unsigned int mtk_m4u_id;
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struct device *m4udev;
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};
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struct mtk_iommu_domain {
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spinlock_t pgtlock; /* lock for page table */
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struct io_pgtable_cfg cfg;
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struct io_pgtable_ops *iop;
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struct iommu_domain domain;
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};
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struct mtk_iommu_data {
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void __iomem *base;
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int irq;
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struct device *dev;
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struct clk *bclk;
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phys_addr_t protect_base; /* protect memory base */
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struct mtk_iommu_suspend_reg reg;
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struct mtk_iommu_domain *m4u_dom;
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struct iommu_group *m4u_group;
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struct mtk_smi_iommu smi_imu; /* SMI larb iommu info */
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};
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static struct iommu_ops mtk_iommu_ops;
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static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
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{
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return container_of(dom, struct mtk_iommu_domain, domain);
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}
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static void mtk_iommu_tlb_flush_all(void *cookie)
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{
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struct mtk_iommu_data *data = cookie;
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writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, data->base + REG_MMU_INV_SEL);
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writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
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wmb(); /* Make sure the tlb flush all done */
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}
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static void mtk_iommu_tlb_add_flush_nosync(unsigned long iova, size_t size,
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size_t granule, bool leaf,
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void *cookie)
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{
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struct mtk_iommu_data *data = cookie;
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writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, data->base + REG_MMU_INV_SEL);
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writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A);
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writel_relaxed(iova + size - 1, data->base + REG_MMU_INVLD_END_A);
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writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE);
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}
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static void mtk_iommu_tlb_sync(void *cookie)
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{
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struct mtk_iommu_data *data = cookie;
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int ret;
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u32 tmp;
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ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, tmp,
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tmp != 0, 10, 100000);
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if (ret) {
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dev_warn(data->dev,
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"Partial TLB flush timed out, falling back to full flush\n");
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mtk_iommu_tlb_flush_all(cookie);
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}
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/* Clear the CPE status */
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writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
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}
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static const struct iommu_gather_ops mtk_iommu_gather_ops = {
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.tlb_flush_all = mtk_iommu_tlb_flush_all,
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.tlb_add_flush = mtk_iommu_tlb_add_flush_nosync,
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.tlb_sync = mtk_iommu_tlb_sync,
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};
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static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
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{
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struct mtk_iommu_data *data = dev_id;
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struct mtk_iommu_domain *dom = data->m4u_dom;
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u32 int_state, regval, fault_iova, fault_pa;
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unsigned int fault_larb, fault_port;
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bool layer, write;
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/* Read error info from registers */
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int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1);
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fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
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layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
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write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
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fault_iova &= F_MMU_FAULT_VA_MSK;
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fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
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regval = readl_relaxed(data->base + REG_MMU_INT_ID);
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fault_larb = F_MMU0_INT_ID_LARB_ID(regval);
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fault_port = F_MMU0_INT_ID_PORT_ID(regval);
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if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
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write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
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dev_err_ratelimited(
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data->dev,
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"fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d layer=%d %s\n",
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int_state, fault_iova, fault_pa, fault_larb, fault_port,
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layer, write ? "write" : "read");
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}
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/* Interrupt clear */
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regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0);
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regval |= F_INT_CLR_BIT;
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writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
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mtk_iommu_tlb_flush_all(data);
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return IRQ_HANDLED;
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}
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static void mtk_iommu_config(struct mtk_iommu_data *data,
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struct device *dev, bool enable)
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{
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struct mtk_iommu_client_priv *head, *cur, *next;
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struct mtk_smi_larb_iommu *larb_mmu;
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unsigned int larbid, portid;
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head = dev->archdata.iommu;
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list_for_each_entry_safe(cur, next, &head->client, client) {
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larbid = MTK_M4U_TO_LARB(cur->mtk_m4u_id);
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portid = MTK_M4U_TO_PORT(cur->mtk_m4u_id);
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larb_mmu = &data->smi_imu.larb_imu[larbid];
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dev_dbg(dev, "%s iommu port: %d\n",
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enable ? "enable" : "disable", portid);
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if (enable)
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larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
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else
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larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
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}
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}
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static int mtk_iommu_domain_finalise(struct mtk_iommu_data *data)
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{
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struct mtk_iommu_domain *dom = data->m4u_dom;
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spin_lock_init(&dom->pgtlock);
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dom->cfg = (struct io_pgtable_cfg) {
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.quirks = IO_PGTABLE_QUIRK_ARM_NS |
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IO_PGTABLE_QUIRK_NO_PERMS |
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IO_PGTABLE_QUIRK_TLBI_ON_MAP,
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.pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
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.ias = 32,
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.oas = 32,
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.tlb = &mtk_iommu_gather_ops,
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.iommu_dev = data->dev,
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};
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dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data);
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if (!dom->iop) {
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dev_err(data->dev, "Failed to alloc io pgtable\n");
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return -EINVAL;
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}
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/* Update our support page sizes bitmap */
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mtk_iommu_ops.pgsize_bitmap = dom->cfg.pgsize_bitmap;
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writel(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0],
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data->base + REG_MMU_PT_BASE_ADDR);
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return 0;
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}
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static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
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{
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struct mtk_iommu_domain *dom;
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if (type != IOMMU_DOMAIN_DMA)
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return NULL;
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dom = kzalloc(sizeof(*dom), GFP_KERNEL);
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if (!dom)
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return NULL;
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if (iommu_get_dma_cookie(&dom->domain)) {
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kfree(dom);
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return NULL;
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}
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dom->domain.geometry.aperture_start = 0;
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dom->domain.geometry.aperture_end = DMA_BIT_MASK(32);
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dom->domain.geometry.force_aperture = true;
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return &dom->domain;
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}
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static void mtk_iommu_domain_free(struct iommu_domain *domain)
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{
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iommu_put_dma_cookie(domain);
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kfree(to_mtk_domain(domain));
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}
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static int mtk_iommu_attach_device(struct iommu_domain *domain,
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struct device *dev)
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{
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struct mtk_iommu_domain *dom = to_mtk_domain(domain);
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struct mtk_iommu_client_priv *priv = dev->archdata.iommu;
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struct mtk_iommu_data *data;
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int ret;
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if (!priv)
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return -ENODEV;
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data = dev_get_drvdata(priv->m4udev);
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if (!data->m4u_dom) {
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data->m4u_dom = dom;
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ret = mtk_iommu_domain_finalise(data);
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if (ret) {
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data->m4u_dom = NULL;
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return ret;
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}
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} else if (data->m4u_dom != dom) {
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/* All the client devices should be in the same m4u domain */
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dev_err(dev, "try to attach into the error iommu domain\n");
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return -EPERM;
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}
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mtk_iommu_config(data, dev, true);
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return 0;
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}
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static void mtk_iommu_detach_device(struct iommu_domain *domain,
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struct device *dev)
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{
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struct mtk_iommu_client_priv *priv = dev->archdata.iommu;
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struct mtk_iommu_data *data;
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if (!priv)
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return;
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data = dev_get_drvdata(priv->m4udev);
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mtk_iommu_config(data, dev, false);
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}
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static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
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phys_addr_t paddr, size_t size, int prot)
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{
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struct mtk_iommu_domain *dom = to_mtk_domain(domain);
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&dom->pgtlock, flags);
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ret = dom->iop->map(dom->iop, iova, paddr, size, prot);
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spin_unlock_irqrestore(&dom->pgtlock, flags);
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return ret;
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}
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static size_t mtk_iommu_unmap(struct iommu_domain *domain,
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unsigned long iova, size_t size)
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{
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struct mtk_iommu_domain *dom = to_mtk_domain(domain);
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unsigned long flags;
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size_t unmapsz;
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spin_lock_irqsave(&dom->pgtlock, flags);
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unmapsz = dom->iop->unmap(dom->iop, iova, size);
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spin_unlock_irqrestore(&dom->pgtlock, flags);
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return unmapsz;
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}
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static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
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dma_addr_t iova)
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{
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struct mtk_iommu_domain *dom = to_mtk_domain(domain);
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unsigned long flags;
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phys_addr_t pa;
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spin_lock_irqsave(&dom->pgtlock, flags);
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pa = dom->iop->iova_to_phys(dom->iop, iova);
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spin_unlock_irqrestore(&dom->pgtlock, flags);
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return pa;
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}
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static int mtk_iommu_add_device(struct device *dev)
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{
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struct iommu_group *group;
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|
||||
if (!dev->archdata.iommu) /* Not a iommu client device */
|
||||
return -ENODEV;
|
||||
|
||||
group = iommu_group_get_for_dev(dev);
|
||||
if (IS_ERR(group))
|
||||
return PTR_ERR(group);
|
||||
|
||||
iommu_group_put(group);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mtk_iommu_remove_device(struct device *dev)
|
||||
{
|
||||
struct mtk_iommu_client_priv *head, *cur, *next;
|
||||
|
||||
head = dev->archdata.iommu;
|
||||
if (!head)
|
||||
return;
|
||||
|
||||
list_for_each_entry_safe(cur, next, &head->client, client) {
|
||||
list_del(&cur->client);
|
||||
kfree(cur);
|
||||
}
|
||||
kfree(head);
|
||||
dev->archdata.iommu = NULL;
|
||||
|
||||
iommu_group_remove_device(dev);
|
||||
}
|
||||
|
||||
static struct iommu_group *mtk_iommu_device_group(struct device *dev)
|
||||
{
|
||||
struct mtk_iommu_data *data;
|
||||
struct mtk_iommu_client_priv *priv;
|
||||
|
||||
priv = dev->archdata.iommu;
|
||||
if (!priv)
|
||||
return ERR_PTR(-ENODEV);
|
||||
|
||||
/* All the client devices are in the same m4u iommu-group */
|
||||
data = dev_get_drvdata(priv->m4udev);
|
||||
if (!data->m4u_group) {
|
||||
data->m4u_group = iommu_group_alloc();
|
||||
if (IS_ERR(data->m4u_group))
|
||||
dev_err(dev, "Failed to allocate M4U IOMMU group\n");
|
||||
}
|
||||
return data->m4u_group;
|
||||
}
|
||||
|
||||
static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
|
||||
{
|
||||
struct mtk_iommu_client_priv *head, *priv, *next;
|
||||
struct platform_device *m4updev;
|
||||
|
||||
if (args->args_count != 1) {
|
||||
dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
|
||||
args->args_count);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!dev->archdata.iommu) {
|
||||
/* Get the m4u device */
|
||||
m4updev = of_find_device_by_node(args->np);
|
||||
of_node_put(args->np);
|
||||
if (WARN_ON(!m4updev))
|
||||
return -EINVAL;
|
||||
|
||||
head = kzalloc(sizeof(*head), GFP_KERNEL);
|
||||
if (!head)
|
||||
return -ENOMEM;
|
||||
|
||||
dev->archdata.iommu = head;
|
||||
INIT_LIST_HEAD(&head->client);
|
||||
head->m4udev = &m4updev->dev;
|
||||
} else {
|
||||
head = dev->archdata.iommu;
|
||||
}
|
||||
|
||||
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
goto err_free_mem;
|
||||
|
||||
priv->mtk_m4u_id = args->args[0];
|
||||
list_add_tail(&priv->client, &head->client);
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_mem:
|
||||
list_for_each_entry_safe(priv, next, &head->client, client)
|
||||
kfree(priv);
|
||||
kfree(head);
|
||||
dev->archdata.iommu = NULL;
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
static struct iommu_ops mtk_iommu_ops = {
|
||||
.domain_alloc = mtk_iommu_domain_alloc,
|
||||
.domain_free = mtk_iommu_domain_free,
|
||||
.attach_dev = mtk_iommu_attach_device,
|
||||
.detach_dev = mtk_iommu_detach_device,
|
||||
.map = mtk_iommu_map,
|
||||
.unmap = mtk_iommu_unmap,
|
||||
.map_sg = default_iommu_map_sg,
|
||||
.iova_to_phys = mtk_iommu_iova_to_phys,
|
||||
.add_device = mtk_iommu_add_device,
|
||||
.remove_device = mtk_iommu_remove_device,
|
||||
.device_group = mtk_iommu_device_group,
|
||||
.of_xlate = mtk_iommu_of_xlate,
|
||||
.pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
|
||||
};
|
||||
|
||||
static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
|
||||
{
|
||||
u32 regval;
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(data->bclk);
|
||||
if (ret) {
|
||||
dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
|
||||
F_MMU_TF_PROTECT_SEL(2);
|
||||
writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
|
||||
|
||||
regval = F_L2_MULIT_HIT_EN |
|
||||
F_TABLE_WALK_FAULT_INT_EN |
|
||||
F_PREETCH_FIFO_OVERFLOW_INT_EN |
|
||||
F_MISS_FIFO_OVERFLOW_INT_EN |
|
||||
F_PREFETCH_FIFO_ERR_INT_EN |
|
||||
F_MISS_FIFO_ERR_INT_EN;
|
||||
writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
|
||||
|
||||
regval = F_INT_TRANSLATION_FAULT |
|
||||
F_INT_MAIN_MULTI_HIT_FAULT |
|
||||
F_INT_INVALID_PA_FAULT |
|
||||
F_INT_ENTRY_REPLACEMENT_FAULT |
|
||||
F_INT_TLB_MISS_FAULT |
|
||||
F_INT_MISS_TRANSACTION_FIFO_FAULT |
|
||||
F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
|
||||
writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
|
||||
|
||||
writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base),
|
||||
data->base + REG_MMU_IVRP_PADDR);
|
||||
|
||||
writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
|
||||
writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE);
|
||||
|
||||
if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
|
||||
dev_name(data->dev), (void *)data)) {
|
||||
writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
|
||||
clk_disable_unprepare(data->bclk);
|
||||
dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int compare_of(struct device *dev, void *data)
|
||||
{
|
||||
return dev->of_node == data;
|
||||
}
|
||||
|
||||
static int mtk_iommu_bind(struct device *dev)
|
||||
{
|
||||
struct mtk_iommu_data *data = dev_get_drvdata(dev);
|
||||
|
||||
return component_bind_all(dev, &data->smi_imu);
|
||||
}
|
||||
|
||||
static void mtk_iommu_unbind(struct device *dev)
|
||||
{
|
||||
struct mtk_iommu_data *data = dev_get_drvdata(dev);
|
||||
|
||||
component_unbind_all(dev, &data->smi_imu);
|
||||
}
|
||||
|
||||
static const struct component_master_ops mtk_iommu_com_ops = {
|
||||
.bind = mtk_iommu_bind,
|
||||
.unbind = mtk_iommu_unbind,
|
||||
};
|
||||
|
||||
static int mtk_iommu_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct mtk_iommu_data *data;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct resource *res;
|
||||
struct component_match *match = NULL;
|
||||
void *protect;
|
||||
unsigned int i, larb_nr;
|
||||
int ret;
|
||||
|
||||
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
data->dev = dev;
|
||||
|
||||
/* Protect memory. HW will access here while translation fault.*/
|
||||
protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL);
|
||||
if (!protect)
|
||||
return -ENOMEM;
|
||||
data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
data->base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(data->base))
|
||||
return PTR_ERR(data->base);
|
||||
|
||||
data->irq = platform_get_irq(pdev, 0);
|
||||
if (data->irq < 0)
|
||||
return data->irq;
|
||||
|
||||
data->bclk = devm_clk_get(dev, "bclk");
|
||||
if (IS_ERR(data->bclk))
|
||||
return PTR_ERR(data->bclk);
|
||||
|
||||
larb_nr = of_count_phandle_with_args(dev->of_node,
|
||||
"mediatek,larbs", NULL);
|
||||
if (larb_nr < 0)
|
||||
return larb_nr;
|
||||
data->smi_imu.larb_nr = larb_nr;
|
||||
|
||||
for (i = 0; i < larb_nr; i++) {
|
||||
struct device_node *larbnode;
|
||||
struct platform_device *plarbdev;
|
||||
|
||||
larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
|
||||
if (!larbnode)
|
||||
return -EINVAL;
|
||||
|
||||
if (!of_device_is_available(larbnode))
|
||||
continue;
|
||||
|
||||
plarbdev = of_find_device_by_node(larbnode);
|
||||
of_node_put(larbnode);
|
||||
if (!plarbdev) {
|
||||
plarbdev = of_platform_device_create(
|
||||
larbnode, NULL,
|
||||
platform_bus_type.dev_root);
|
||||
if (IS_ERR(plarbdev))
|
||||
return -EPROBE_DEFER;
|
||||
}
|
||||
data->smi_imu.larb_imu[i].dev = &plarbdev->dev;
|
||||
|
||||
component_match_add(dev, &match, compare_of, larbnode);
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, data);
|
||||
|
||||
ret = mtk_iommu_hw_init(data);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (!iommu_present(&platform_bus_type))
|
||||
bus_set_iommu(&platform_bus_type, &mtk_iommu_ops);
|
||||
|
||||
return component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
|
||||
}
|
||||
|
||||
static int mtk_iommu_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct mtk_iommu_data *data = platform_get_drvdata(pdev);
|
||||
|
||||
if (iommu_present(&platform_bus_type))
|
||||
bus_set_iommu(&platform_bus_type, NULL);
|
||||
|
||||
free_io_pgtable_ops(data->m4u_dom->iop);
|
||||
clk_disable_unprepare(data->bclk);
|
||||
devm_free_irq(&pdev->dev, data->irq, data);
|
||||
component_master_del(&pdev->dev, &mtk_iommu_com_ops);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_iommu_suspend(struct device *dev)
|
||||
{
|
||||
struct mtk_iommu_data *data = dev_get_drvdata(dev);
|
||||
struct mtk_iommu_suspend_reg *reg = &data->reg;
|
||||
void __iomem *base = data->base;
|
||||
|
||||
reg->standard_axi_mode = readl_relaxed(base +
|
||||
REG_MMU_STANDARD_AXI_MODE);
|
||||
reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
|
||||
reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
|
||||
reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0);
|
||||
reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_iommu_resume(struct device *dev)
|
||||
{
|
||||
struct mtk_iommu_data *data = dev_get_drvdata(dev);
|
||||
struct mtk_iommu_suspend_reg *reg = &data->reg;
|
||||
void __iomem *base = data->base;
|
||||
|
||||
writel_relaxed(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0],
|
||||
base + REG_MMU_PT_BASE_ADDR);
|
||||
writel_relaxed(reg->standard_axi_mode,
|
||||
base + REG_MMU_STANDARD_AXI_MODE);
|
||||
writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
|
||||
writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
|
||||
writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
|
||||
writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
|
||||
writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base),
|
||||
base + REG_MMU_IVRP_PADDR);
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct dev_pm_ops mtk_iommu_pm_ops = {
|
||||
SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
|
||||
};
|
||||
|
||||
static const struct of_device_id mtk_iommu_of_ids[] = {
|
||||
{ .compatible = "mediatek,mt8173-m4u", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver mtk_iommu_driver = {
|
||||
.probe = mtk_iommu_probe,
|
||||
.remove = mtk_iommu_remove,
|
||||
.driver = {
|
||||
.name = "mtk-iommu",
|
||||
.of_match_table = mtk_iommu_of_ids,
|
||||
.pm = &mtk_iommu_pm_ops,
|
||||
}
|
||||
};
|
||||
|
||||
static int mtk_iommu_init_fn(struct device_node *np)
|
||||
{
|
||||
int ret;
|
||||
struct platform_device *pdev;
|
||||
|
||||
pdev = of_platform_device_create(np, NULL, platform_bus_type.dev_root);
|
||||
if (IS_ERR(pdev))
|
||||
return PTR_ERR(pdev);
|
||||
|
||||
ret = platform_driver_register(&mtk_iommu_driver);
|
||||
if (ret) {
|
||||
pr_err("%s: Failed to register driver\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
of_iommu_set_ops(np, &mtk_iommu_ops);
|
||||
return 0;
|
||||
}
|
||||
|
||||
IOMMU_OF_DECLARE(mtkm4u, "mediatek,mt8173-m4u", mtk_iommu_init_fn);
|
||||
Loading…
Reference in a new issue