forked from mirrors/linux
		
	ice: xsk: Improve AF_XDP ZC Tx and use batching API
Apply the logic that was done for regular XDP from commit 9610bd988d
("ice: optimize XDP_TX workloads") to the ZC side of the driver. On top
of that, introduce batching to Tx that is inspired by i40e's
implementation with adjustments to the cleaning logic - take into the
account NAPI budget in ice_clean_xdp_irq_zc().
Separating the stats structs onto separate cache lines seemed to improve
the performance.
Signed-off-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Reviewed-by: Alexander Lobakin <alexandr.lobakin@intel.com>
Link: https://lore.kernel.org/bpf/20220125160446.78976-8-maciej.fijalkowski@intel.com
			
			
This commit is contained in:
		
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						commit
						126cdfe100
					
				
					 4 changed files with 199 additions and 110 deletions
				
			
		| 
						 | 
					@ -1462,7 +1462,7 @@ int ice_napi_poll(struct napi_struct *napi, int budget)
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		bool wd;
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							bool wd;
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		if (tx_ring->xsk_pool)
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							if (tx_ring->xsk_pool)
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			wd = ice_clean_tx_irq_zc(tx_ring, budget);
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								wd = ice_xmit_zc(tx_ring, ICE_DESC_UNUSED(tx_ring), budget);
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		else if (ice_ring_is_xdp(tx_ring))
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							else if (ice_ring_is_xdp(tx_ring))
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			wd = true;
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								wd = true;
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		else
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							else
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					@ -322,17 +322,17 @@ struct ice_tx_ring {
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	u16 count;			/* Number of descriptors */
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						u16 count;			/* Number of descriptors */
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	u16 q_index;			/* Queue number of ring */
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						u16 q_index;			/* Queue number of ring */
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	/* stats structs */
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						/* stats structs */
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						struct ice_txq_stats tx_stats;
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						/* CL3 - 3rd cacheline starts here */
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	struct ice_q_stats	stats;
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						struct ice_q_stats	stats;
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	struct u64_stats_sync syncp;
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						struct u64_stats_sync syncp;
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	struct ice_txq_stats tx_stats;
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	/* CL3 - 3rd cacheline starts here */
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	struct rcu_head rcu;		/* to avoid race on free */
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						struct rcu_head rcu;		/* to avoid race on free */
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	DECLARE_BITMAP(xps_state, ICE_TX_NBITS);	/* XPS Config State */
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						DECLARE_BITMAP(xps_state, ICE_TX_NBITS);	/* XPS Config State */
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	struct ice_channel *ch;
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						struct ice_channel *ch;
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	struct ice_ptp_tx *tx_tstamps;
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						struct ice_ptp_tx *tx_tstamps;
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	spinlock_t tx_lock;
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						spinlock_t tx_lock;
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	u32 txq_teid;			/* Added Tx queue TEID */
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						u32 txq_teid;			/* Added Tx queue TEID */
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						/* CL4 - 4th cacheline starts here */
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#define ICE_TX_FLAGS_RING_XDP		BIT(0)
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					#define ICE_TX_FLAGS_RING_XDP		BIT(0)
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	u8 flags;
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						u8 flags;
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	u8 dcb_tc;			/* Traffic class of ring */
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						u8 dcb_tc;			/* Traffic class of ring */
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					@ -678,58 +678,6 @@ int ice_clean_rx_irq_zc(struct ice_rx_ring *rx_ring, int budget)
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	return failure ? budget : (int)total_rx_packets;
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						return failure ? budget : (int)total_rx_packets;
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}
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					}
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/**
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 * ice_xmit_zc - Completes AF_XDP entries, and cleans XDP entries
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 * @xdp_ring: XDP Tx ring
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 * @budget: max number of frames to xmit
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 *
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 * Returns true if cleanup/transmission is done.
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 */
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static bool ice_xmit_zc(struct ice_tx_ring *xdp_ring, int budget)
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{
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	struct ice_tx_desc *tx_desc = NULL;
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	bool work_done = true;
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	struct xdp_desc desc;
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	dma_addr_t dma;
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	while (likely(budget-- > 0)) {
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		struct ice_tx_buf *tx_buf;
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		if (unlikely(!ICE_DESC_UNUSED(xdp_ring))) {
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			xdp_ring->tx_stats.tx_busy++;
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			work_done = false;
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			break;
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		}
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		tx_buf = &xdp_ring->tx_buf[xdp_ring->next_to_use];
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		if (!xsk_tx_peek_desc(xdp_ring->xsk_pool, &desc))
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			break;
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		dma = xsk_buff_raw_get_dma(xdp_ring->xsk_pool, desc.addr);
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		xsk_buff_raw_dma_sync_for_device(xdp_ring->xsk_pool, dma,
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						 desc.len);
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		tx_buf->bytecount = desc.len;
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		tx_desc = ICE_TX_DESC(xdp_ring, xdp_ring->next_to_use);
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		tx_desc->buf_addr = cpu_to_le64(dma);
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		tx_desc->cmd_type_offset_bsz =
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			ice_build_ctob(ICE_TXD_LAST_DESC_CMD, 0, desc.len, 0);
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		xdp_ring->next_to_use++;
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		if (xdp_ring->next_to_use == xdp_ring->count)
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			xdp_ring->next_to_use = 0;
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	}
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	if (tx_desc) {
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		ice_xdp_ring_update_tail(xdp_ring);
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		xsk_tx_release(xdp_ring->xsk_pool);
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	}
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	return budget > 0 && work_done;
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}
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/**
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					/**
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 * ice_clean_xdp_tx_buf - Free and unmap XDP Tx buffer
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					 * ice_clean_xdp_tx_buf - Free and unmap XDP Tx buffer
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 * @xdp_ring: XDP Tx ring
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					 * @xdp_ring: XDP Tx ring
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					@ -745,68 +693,198 @@ ice_clean_xdp_tx_buf(struct ice_tx_ring *xdp_ring, struct ice_tx_buf *tx_buf)
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}
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					}
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/**
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					/**
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 * ice_clean_tx_irq_zc - Completes AF_XDP entries, and cleans XDP entries
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					 * ice_clean_xdp_irq_zc - Reclaim resources after transmit completes on XDP ring
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 * @xdp_ring: XDP Tx ring
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					 * @xdp_ring: XDP ring to clean
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 * @budget: NAPI budget
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					 * @napi_budget: amount of descriptors that NAPI allows us to clean
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 *
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					 *
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 * Returns true if cleanup/tranmission is done.
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					 * Returns count of cleaned descriptors
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 */
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					 */
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bool ice_clean_tx_irq_zc(struct ice_tx_ring *xdp_ring, int budget)
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					static u16 ice_clean_xdp_irq_zc(struct ice_tx_ring *xdp_ring, int napi_budget)
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{
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					{
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	int total_packets = 0, total_bytes = 0;
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						u16 tx_thresh = ICE_RING_QUARTER(xdp_ring);
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	s16 ntc = xdp_ring->next_to_clean;
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						int budget = napi_budget / tx_thresh;
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	struct ice_tx_desc *tx_desc;
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						u16 ntc = xdp_ring->next_to_clean;
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	struct ice_tx_buf *tx_buf;
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						u16 next_dd = xdp_ring->next_dd;
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	u32 xsk_frames = 0;
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						u16 cleared_dds = 0;
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	bool xmit_done;
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	tx_desc = ICE_TX_DESC(xdp_ring, ntc);
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	tx_buf = &xdp_ring->tx_buf[ntc];
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	ntc -= xdp_ring->count;
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	do {
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						do {
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		if (!(tx_desc->cmd_type_offset_bsz &
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							struct ice_tx_desc *next_dd_desc;
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		      cpu_to_le64(ICE_TX_DESC_DTYPE_DESC_DONE)))
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							u16 desc_cnt = xdp_ring->count;
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							struct ice_tx_buf *tx_buf;
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							u32 xsk_frames;
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							u16 i;
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							next_dd_desc = ICE_TX_DESC(xdp_ring, next_dd);
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							if (!(next_dd_desc->cmd_type_offset_bsz &
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							    cpu_to_le64(ICE_TX_DESC_DTYPE_DESC_DONE)))
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			break;
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								break;
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		total_bytes += tx_buf->bytecount;
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							cleared_dds++;
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		total_packets++;
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							xsk_frames = 0;
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		if (tx_buf->raw_buf) {
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							for (i = 0; i < tx_thresh; i++) {
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			ice_clean_xdp_tx_buf(xdp_ring, tx_buf);
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								tx_buf = &xdp_ring->tx_buf[ntc];
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			tx_buf->raw_buf = NULL;
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		} else {
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								if (tx_buf->raw_buf) {
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			xsk_frames++;
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									ice_clean_xdp_tx_buf(xdp_ring, tx_buf);
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									tx_buf->raw_buf = NULL;
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								} else {
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									xsk_frames++;
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								}
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								ntc++;
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								if (ntc >= xdp_ring->count)
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									ntc = 0;
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		}
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							}
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							if (xsk_frames)
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								xsk_tx_completed(xdp_ring->xsk_pool, xsk_frames);
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							next_dd_desc->cmd_type_offset_bsz = 0;
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							next_dd = next_dd + tx_thresh;
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							if (next_dd >= desc_cnt)
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								next_dd = tx_thresh - 1;
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						} while (budget--);
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		tx_desc->cmd_type_offset_bsz = 0;
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		tx_buf++;
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		tx_desc++;
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		ntc++;
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		if (unlikely(!ntc)) {
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			ntc -= xdp_ring->count;
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			tx_buf = xdp_ring->tx_buf;
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			tx_desc = ICE_TX_DESC(xdp_ring, 0);
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		}
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		prefetch(tx_desc);
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	} while (likely(--budget));
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	ntc += xdp_ring->count;
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	xdp_ring->next_to_clean = ntc;
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						xdp_ring->next_to_clean = ntc;
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						xdp_ring->next_dd = next_dd;
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	if (xsk_frames)
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						return cleared_dds * tx_thresh;
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		xsk_tx_completed(xdp_ring->xsk_pool, xsk_frames);
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					}
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					/**
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					 * ice_xmit_pkt - produce a single HW Tx descriptor out of AF_XDP descriptor
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					 * @xdp_ring: XDP ring to produce the HW Tx descriptor on
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					 * @desc: AF_XDP descriptor to pull the DMA address and length from
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					 * @total_bytes: bytes accumulator that will be used for stats update
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					 */
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					static void ice_xmit_pkt(struct ice_tx_ring *xdp_ring, struct xdp_desc *desc,
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								 unsigned int *total_bytes)
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					{
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						struct ice_tx_desc *tx_desc;
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						dma_addr_t dma;
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						dma = xsk_buff_raw_get_dma(xdp_ring->xsk_pool, desc->addr);
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						xsk_buff_raw_dma_sync_for_device(xdp_ring->xsk_pool, dma, desc->len);
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						tx_desc = ICE_TX_DESC(xdp_ring, xdp_ring->next_to_use++);
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						tx_desc->buf_addr = cpu_to_le64(dma);
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						tx_desc->cmd_type_offset_bsz = ice_build_ctob(ICE_TX_DESC_CMD_EOP,
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											      0, desc->len, 0);
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						*total_bytes += desc->len;
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					}
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					/**
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					 * ice_xmit_pkt_batch - produce a batch of HW Tx descriptors out of AF_XDP descriptors
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					 * @xdp_ring: XDP ring to produce the HW Tx descriptors on
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					 * @descs: AF_XDP descriptors to pull the DMA addresses and lengths from
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					 * @total_bytes: bytes accumulator that will be used for stats update
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					 */
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					static void ice_xmit_pkt_batch(struct ice_tx_ring *xdp_ring, struct xdp_desc *descs,
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								       unsigned int *total_bytes)
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					{
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						u16 tx_thresh = ICE_RING_QUARTER(xdp_ring);
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						u16 ntu = xdp_ring->next_to_use;
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						struct ice_tx_desc *tx_desc;
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						u32 i;
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						loop_unrolled_for(i = 0; i < PKTS_PER_BATCH; i++) {
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							dma_addr_t dma;
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							dma = xsk_buff_raw_get_dma(xdp_ring->xsk_pool, descs[i].addr);
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							xsk_buff_raw_dma_sync_for_device(xdp_ring->xsk_pool, dma, descs[i].len);
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							tx_desc = ICE_TX_DESC(xdp_ring, ntu++);
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							tx_desc->buf_addr = cpu_to_le64(dma);
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							tx_desc->cmd_type_offset_bsz = ice_build_ctob(ICE_TX_DESC_CMD_EOP,
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												      0, descs[i].len, 0);
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							*total_bytes += descs[i].len;
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						}
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						xdp_ring->next_to_use = ntu;
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						if (xdp_ring->next_to_use > xdp_ring->next_rs) {
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							tx_desc = ICE_TX_DESC(xdp_ring, xdp_ring->next_rs);
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							tx_desc->cmd_type_offset_bsz |=
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								cpu_to_le64(ICE_TX_DESC_CMD_RS << ICE_TXD_QW1_CMD_S);
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							xdp_ring->next_rs += tx_thresh;
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						}
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					}
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					/**
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					 * ice_fill_tx_hw_ring - produce the number of Tx descriptors onto ring
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					 * @xdp_ring: XDP ring to produce the HW Tx descriptors on
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					 * @descs: AF_XDP descriptors to pull the DMA addresses and lengths from
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					 * @nb_pkts: count of packets to be send
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					 * @total_bytes: bytes accumulator that will be used for stats update
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					 */
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					static void ice_fill_tx_hw_ring(struct ice_tx_ring *xdp_ring, struct xdp_desc *descs,
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									u32 nb_pkts, unsigned int *total_bytes)
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					{
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						u16 tx_thresh = ICE_RING_QUARTER(xdp_ring);
 | 
				
			||||||
 | 
						u32 batched, leftover, i;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						batched = ALIGN_DOWN(nb_pkts, PKTS_PER_BATCH);
 | 
				
			||||||
 | 
						leftover = nb_pkts & (PKTS_PER_BATCH - 1);
 | 
				
			||||||
 | 
						for (i = 0; i < batched; i += PKTS_PER_BATCH)
 | 
				
			||||||
 | 
							ice_xmit_pkt_batch(xdp_ring, &descs[i], total_bytes);
 | 
				
			||||||
 | 
						for (; i < batched + leftover; i++)
 | 
				
			||||||
 | 
							ice_xmit_pkt(xdp_ring, &descs[i], total_bytes);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						if (xdp_ring->next_to_use > xdp_ring->next_rs) {
 | 
				
			||||||
 | 
							struct ice_tx_desc *tx_desc;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
							tx_desc = ICE_TX_DESC(xdp_ring, xdp_ring->next_rs);
 | 
				
			||||||
 | 
							tx_desc->cmd_type_offset_bsz |=
 | 
				
			||||||
 | 
								cpu_to_le64(ICE_TX_DESC_CMD_RS << ICE_TXD_QW1_CMD_S);
 | 
				
			||||||
 | 
							xdp_ring->next_rs += tx_thresh;
 | 
				
			||||||
 | 
						}
 | 
				
			||||||
 | 
					}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					/**
 | 
				
			||||||
 | 
					 * ice_xmit_zc - take entries from XSK Tx ring and place them onto HW Tx ring
 | 
				
			||||||
 | 
					 * @xdp_ring: XDP ring to produce the HW Tx descriptors on
 | 
				
			||||||
 | 
					 * @budget: number of free descriptors on HW Tx ring that can be used
 | 
				
			||||||
 | 
					 * @napi_budget: amount of descriptors that NAPI allows us to clean
 | 
				
			||||||
 | 
					 *
 | 
				
			||||||
 | 
					 * Returns true if there is no more work that needs to be done, false otherwise
 | 
				
			||||||
 | 
					 */
 | 
				
			||||||
 | 
					bool ice_xmit_zc(struct ice_tx_ring *xdp_ring, u32 budget, int napi_budget)
 | 
				
			||||||
 | 
					{
 | 
				
			||||||
 | 
						struct xdp_desc *descs = xdp_ring->xsk_pool->tx_descs;
 | 
				
			||||||
 | 
						u16 tx_thresh = ICE_RING_QUARTER(xdp_ring);
 | 
				
			||||||
 | 
						u32 nb_pkts, nb_processed = 0;
 | 
				
			||||||
 | 
						unsigned int total_bytes = 0;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						if (budget < tx_thresh)
 | 
				
			||||||
 | 
							budget += ice_clean_xdp_irq_zc(xdp_ring, napi_budget);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						nb_pkts = xsk_tx_peek_release_desc_batch(xdp_ring->xsk_pool, budget);
 | 
				
			||||||
 | 
						if (!nb_pkts)
 | 
				
			||||||
 | 
							return true;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						if (xdp_ring->next_to_use + nb_pkts >= xdp_ring->count) {
 | 
				
			||||||
 | 
							struct ice_tx_desc *tx_desc;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
							nb_processed = xdp_ring->count - xdp_ring->next_to_use;
 | 
				
			||||||
 | 
							ice_fill_tx_hw_ring(xdp_ring, descs, nb_processed, &total_bytes);
 | 
				
			||||||
 | 
							tx_desc = ICE_TX_DESC(xdp_ring, xdp_ring->next_rs);
 | 
				
			||||||
 | 
							tx_desc->cmd_type_offset_bsz |=
 | 
				
			||||||
 | 
								cpu_to_le64(ICE_TX_DESC_CMD_RS << ICE_TXD_QW1_CMD_S);
 | 
				
			||||||
 | 
							xdp_ring->next_rs = tx_thresh - 1;
 | 
				
			||||||
 | 
							xdp_ring->next_to_use = 0;
 | 
				
			||||||
 | 
						}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						ice_fill_tx_hw_ring(xdp_ring, &descs[nb_processed], nb_pkts - nb_processed,
 | 
				
			||||||
 | 
								    &total_bytes);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						ice_xdp_ring_update_tail(xdp_ring);
 | 
				
			||||||
 | 
						ice_update_tx_ring_stats(xdp_ring, nb_pkts, total_bytes);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	if (xsk_uses_need_wakeup(xdp_ring->xsk_pool))
 | 
						if (xsk_uses_need_wakeup(xdp_ring->xsk_pool))
 | 
				
			||||||
		xsk_set_tx_need_wakeup(xdp_ring->xsk_pool);
 | 
							xsk_set_tx_need_wakeup(xdp_ring->xsk_pool);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	ice_update_tx_ring_stats(xdp_ring, total_packets, total_bytes);
 | 
						return nb_pkts < budget;
 | 
				
			||||||
	xmit_done = ice_xmit_zc(xdp_ring, ICE_DFLT_IRQ_WORK);
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
	return budget > 0 && xmit_done;
 | 
					 | 
				
			||||||
}
 | 
					}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
/**
 | 
					/**
 | 
				
			||||||
| 
						 | 
					
 | 
				
			||||||
| 
						 | 
					@ -6,19 +6,37 @@
 | 
				
			||||||
#include "ice_txrx.h"
 | 
					#include "ice_txrx.h"
 | 
				
			||||||
#include "ice.h"
 | 
					#include "ice.h"
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#define PKTS_PER_BATCH 8
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#ifdef __clang__
 | 
				
			||||||
 | 
					#define loop_unrolled_for _Pragma("clang loop unroll_count(8)") for
 | 
				
			||||||
 | 
					#elif __GNUC__ >= 4
 | 
				
			||||||
 | 
					#define loop_unrolled_for _Pragma("GCC unroll 8") for
 | 
				
			||||||
 | 
					#else
 | 
				
			||||||
 | 
					#define loop_unrolled_for for
 | 
				
			||||||
 | 
					#endif
 | 
				
			||||||
 | 
					
 | 
				
			||||||
struct ice_vsi;
 | 
					struct ice_vsi;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
#ifdef CONFIG_XDP_SOCKETS
 | 
					#ifdef CONFIG_XDP_SOCKETS
 | 
				
			||||||
int ice_xsk_pool_setup(struct ice_vsi *vsi, struct xsk_buff_pool *pool,
 | 
					int ice_xsk_pool_setup(struct ice_vsi *vsi, struct xsk_buff_pool *pool,
 | 
				
			||||||
		       u16 qid);
 | 
							       u16 qid);
 | 
				
			||||||
int ice_clean_rx_irq_zc(struct ice_rx_ring *rx_ring, int budget);
 | 
					int ice_clean_rx_irq_zc(struct ice_rx_ring *rx_ring, int budget);
 | 
				
			||||||
bool ice_clean_tx_irq_zc(struct ice_tx_ring *xdp_ring, int budget);
 | 
					 | 
				
			||||||
int ice_xsk_wakeup(struct net_device *netdev, u32 queue_id, u32 flags);
 | 
					int ice_xsk_wakeup(struct net_device *netdev, u32 queue_id, u32 flags);
 | 
				
			||||||
bool ice_alloc_rx_bufs_zc(struct ice_rx_ring *rx_ring, u16 count);
 | 
					bool ice_alloc_rx_bufs_zc(struct ice_rx_ring *rx_ring, u16 count);
 | 
				
			||||||
bool ice_xsk_any_rx_ring_ena(struct ice_vsi *vsi);
 | 
					bool ice_xsk_any_rx_ring_ena(struct ice_vsi *vsi);
 | 
				
			||||||
void ice_xsk_clean_rx_ring(struct ice_rx_ring *rx_ring);
 | 
					void ice_xsk_clean_rx_ring(struct ice_rx_ring *rx_ring);
 | 
				
			||||||
void ice_xsk_clean_xdp_ring(struct ice_tx_ring *xdp_ring);
 | 
					void ice_xsk_clean_xdp_ring(struct ice_tx_ring *xdp_ring);
 | 
				
			||||||
 | 
					bool ice_xmit_zc(struct ice_tx_ring *xdp_ring, u32 budget, int napi_budget);
 | 
				
			||||||
#else
 | 
					#else
 | 
				
			||||||
 | 
					static inline bool
 | 
				
			||||||
 | 
					ice_xmit_zc(struct ice_tx_ring __always_unused *xdp_ring,
 | 
				
			||||||
 | 
						    u32 __always_unused budget,
 | 
				
			||||||
 | 
						    int __always_unused napi_budget)
 | 
				
			||||||
 | 
					{
 | 
				
			||||||
 | 
						return false;
 | 
				
			||||||
 | 
					}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
static inline int
 | 
					static inline int
 | 
				
			||||||
ice_xsk_pool_setup(struct ice_vsi __always_unused *vsi,
 | 
					ice_xsk_pool_setup(struct ice_vsi __always_unused *vsi,
 | 
				
			||||||
		   struct xsk_buff_pool __always_unused *pool,
 | 
							   struct xsk_buff_pool __always_unused *pool,
 | 
				
			||||||
| 
						 | 
					@ -34,13 +52,6 @@ ice_clean_rx_irq_zc(struct ice_rx_ring __always_unused *rx_ring,
 | 
				
			||||||
	return 0;
 | 
						return 0;
 | 
				
			||||||
}
 | 
					}
 | 
				
			||||||
 | 
					
 | 
				
			||||||
static inline bool
 | 
					 | 
				
			||||||
ice_clean_tx_irq_zc(struct ice_tx_ring __always_unused *xdp_ring,
 | 
					 | 
				
			||||||
		    int __always_unused budget)
 | 
					 | 
				
			||||||
{
 | 
					 | 
				
			||||||
	return false;
 | 
					 | 
				
			||||||
}
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
static inline bool
 | 
					static inline bool
 | 
				
			||||||
ice_alloc_rx_bufs_zc(struct ice_rx_ring __always_unused *rx_ring,
 | 
					ice_alloc_rx_bufs_zc(struct ice_rx_ring __always_unused *rx_ring,
 | 
				
			||||||
		     u16 __always_unused count)
 | 
							     u16 __always_unused count)
 | 
				
			||||||
| 
						 | 
					
 | 
				
			||||||
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		Reference in a new issue