forked from mirrors/linux
drm/imagination: Add RISC-V firmware processor support
Newer PowerVR GPUs (such as the BXS-4-64 MC1) use a RISC-V firmware processor instead of the previous MIPS or META. The current version of this patch depends on a patch[1] which exists in drm-misc-fixes, but has not yet made it back to drm-misc-next (the target of this patch). That patch adds the function pvr_vm_unmap_obj() which is used here. [1]: https://lore.kernel.org/r/20250226-hold-drm_gem_gpuva-lock-for-unmap-v2-1-3fdacded227f@imgtec.com Signed-off-by: Sarah Walker <sarah.walker@imgtec.com> Reviewed-by: Frank Binns <frank.binns@imgtec.com> Link: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-14-eda620c5865f@imgtec.com Signed-off-by: Matt Coster <matt.coster@imgtec.com>
This commit is contained in:
Sarah Walker
Matt Coster
parent
f48485ab50
commit
171f378d2a
6 changed files with 244 additions and 8 deletions
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@ -12,6 +12,7 @@ powervr-y := \
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pvr_fw.o \
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pvr_fw_meta.o \
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pvr_fw_mips.o \
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pvr_fw_riscv.o \
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pvr_fw_startstop.o \
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pvr_fw_trace.o \
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pvr_fw_util.o \
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@ -941,7 +941,7 @@ pvr_fw_init(struct pvr_device *pvr_dev)
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static const struct pvr_fw_defs *fw_defs[PVR_FW_PROCESSOR_TYPE_COUNT] = {
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[PVR_FW_PROCESSOR_TYPE_META] = &pvr_fw_defs_meta,
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[PVR_FW_PROCESSOR_TYPE_MIPS] = &pvr_fw_defs_mips,
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[PVR_FW_PROCESSOR_TYPE_RISCV] = NULL,
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[PVR_FW_PROCESSOR_TYPE_RISCV] = &pvr_fw_defs_riscv,
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};
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u32 kccb_size_log2 = ROGUE_FWIF_KCCB_NUMCMDS_LOG2_DEFAULT;
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@ -954,13 +954,6 @@ pvr_fw_init(struct pvr_device *pvr_dev)
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fw_dev->defs = fw_defs[fw_dev->processor_type];
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/*
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* Not all firmware processor types are currently supported.
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* Once they are, this check can be removed.
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*/
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if (!fw_dev->defs)
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return -EINVAL;
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err = fw_dev->defs->init(pvr_dev);
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if (err)
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return err;
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@ -1466,6 +1459,15 @@ void pvr_fw_object_get_fw_addr_offset(struct pvr_fw_object *fw_obj, u32 offset,
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*fw_addr_out = pvr_dev->fw_dev.defs->get_fw_addr_with_offset(fw_obj, offset);
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}
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u64
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pvr_fw_obj_get_gpu_addr(struct pvr_fw_object *fw_obj)
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{
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struct pvr_device *pvr_dev = to_pvr_device(gem_from_pvr_gem(fw_obj->gem)->dev);
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struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev;
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return fw_dev->fw_heap_info.gpu_addr + fw_obj->fw_addr_offset;
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}
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/*
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* pvr_fw_hard_reset() - Re-initialise the FW code and data segments, and reset all global FW
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* structures
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@ -392,6 +392,7 @@ enum pvr_fw_processor_type {
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extern const struct pvr_fw_defs pvr_fw_defs_meta;
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extern const struct pvr_fw_defs pvr_fw_defs_mips;
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extern const struct pvr_fw_defs pvr_fw_defs_riscv;
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int pvr_fw_validate_init_device_info(struct pvr_device *pvr_dev);
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int pvr_fw_init(struct pvr_device *pvr_dev);
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@ -478,6 +479,15 @@ pvr_fw_object_get_fw_addr(struct pvr_fw_object *fw_obj, u32 *fw_addr_out)
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pvr_fw_object_get_fw_addr_offset(fw_obj, 0, fw_addr_out);
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}
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u64
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pvr_fw_obj_get_gpu_addr(struct pvr_fw_object *fw_obj);
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static __always_inline size_t
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pvr_fw_obj_get_object_size(struct pvr_fw_object *fw_obj)
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{
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return pvr_gem_object_size(fw_obj->gem);
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}
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/* Util functions defined in pvr_fw_util.c. These are intended for use in pvr_fw_<arch>.c files. */
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int
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pvr_fw_process_elf_command_stream(struct pvr_device *pvr_dev, const u8 *fw, u8 *fw_code_ptr,
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165
drivers/gpu/drm/imagination/pvr_fw_riscv.c
Normal file
165
drivers/gpu/drm/imagination/pvr_fw_riscv.c
Normal file
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@ -0,0 +1,165 @@
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// SPDX-License-Identifier: GPL-2.0 OR MIT
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/* Copyright (c) 2024 Imagination Technologies Ltd. */
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#include "pvr_device.h"
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#include "pvr_fw.h"
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#include "pvr_fw_info.h"
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#include "pvr_fw_mips.h"
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#include "pvr_gem.h"
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#include "pvr_rogue_cr_defs.h"
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#include "pvr_rogue_riscv.h"
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#include "pvr_vm.h"
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#include <linux/compiler.h>
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#include <linux/delay.h>
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#include <linux/firmware.h>
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#include <linux/ktime.h>
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#include <linux/types.h>
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#define ROGUE_FW_HEAP_RISCV_SHIFT 25 /* 32 MB */
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#define ROGUE_FW_HEAP_RISCV_SIZE (1u << ROGUE_FW_HEAP_RISCV_SHIFT)
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static int
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pvr_riscv_wrapper_init(struct pvr_device *pvr_dev)
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{
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const u64 common_opts =
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((u64)(ROGUE_FW_HEAP_RISCV_SIZE >> FWCORE_ADDR_REMAP_CONFIG0_SIZE_ALIGNSHIFT)
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<< ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_SIZE_SHIFT) |
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((u64)MMU_CONTEXT_MAPPING_FWPRIV
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<< FWCORE_ADDR_REMAP_CONFIG0_MMU_CONTEXT_SHIFT);
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u64 code_addr = pvr_fw_obj_get_gpu_addr(pvr_dev->fw_dev.mem.code_obj);
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u64 data_addr = pvr_fw_obj_get_gpu_addr(pvr_dev->fw_dev.mem.data_obj);
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/* This condition allows us to OR the addresses into the register directly. */
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static_assert(ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_SHIFT ==
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ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_ALIGNSHIFT);
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WARN_ON(code_addr & ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_CLRMSK);
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WARN_ON(data_addr & ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_CLRMSK);
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pvr_cr_write64(pvr_dev, ROGUE_RISCVFW_REGION_REMAP_CR(BOOTLDR_CODE),
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code_addr | common_opts | ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_FETCH_EN_EN);
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pvr_cr_write64(pvr_dev, ROGUE_RISCVFW_REGION_REMAP_CR(BOOTLDR_DATA),
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data_addr | common_opts |
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ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_LOAD_STORE_EN_EN);
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/* Garten IDLE bit controlled by RISC-V. */
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pvr_cr_write64(pvr_dev, ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG,
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ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_META);
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return 0;
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}
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struct rogue_riscv_fw_boot_data {
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u64 coremem_code_dev_vaddr;
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u64 coremem_data_dev_vaddr;
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u32 coremem_code_fw_addr;
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u32 coremem_data_fw_addr;
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u32 coremem_code_size;
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u32 coremem_data_size;
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u32 flags;
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u32 reserved;
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};
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static int
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pvr_riscv_fw_process(struct pvr_device *pvr_dev, const u8 *fw,
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u8 *fw_code_ptr, u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr,
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u32 core_code_alloc_size)
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{
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struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev;
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struct pvr_fw_mem *fw_mem = &fw_dev->mem;
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struct rogue_riscv_fw_boot_data *boot_data;
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int err;
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err = pvr_fw_process_elf_command_stream(pvr_dev, fw, fw_code_ptr, fw_data_ptr,
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fw_core_code_ptr, fw_core_data_ptr);
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if (err)
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goto err_out;
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boot_data = (struct rogue_riscv_fw_boot_data *)fw_data_ptr;
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if (fw_mem->core_code_obj) {
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boot_data->coremem_code_dev_vaddr = pvr_fw_obj_get_gpu_addr(fw_mem->core_code_obj);
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pvr_fw_object_get_fw_addr(fw_mem->core_code_obj, &boot_data->coremem_code_fw_addr);
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boot_data->coremem_code_size = pvr_fw_obj_get_object_size(fw_mem->core_code_obj);
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}
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if (fw_mem->core_data_obj) {
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boot_data->coremem_data_dev_vaddr = pvr_fw_obj_get_gpu_addr(fw_mem->core_data_obj);
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pvr_fw_object_get_fw_addr(fw_mem->core_data_obj, &boot_data->coremem_data_fw_addr);
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boot_data->coremem_data_size = pvr_fw_obj_get_object_size(fw_mem->core_data_obj);
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}
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return 0;
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err_out:
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return err;
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}
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static int
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pvr_riscv_init(struct pvr_device *pvr_dev)
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{
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pvr_fw_heap_info_init(pvr_dev, ROGUE_FW_HEAP_RISCV_SHIFT, 0);
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return 0;
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}
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static u32
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pvr_riscv_get_fw_addr_with_offset(struct pvr_fw_object *fw_obj, u32 offset)
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{
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u32 fw_addr = fw_obj->fw_addr_offset + offset;
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/* RISC-V cacheability is determined by address. */
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if (fw_obj->gem->flags & PVR_BO_FW_FLAGS_DEVICE_UNCACHED)
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fw_addr |= ROGUE_RISCVFW_REGION_BASE(SHARED_UNCACHED_DATA);
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else
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fw_addr |= ROGUE_RISCVFW_REGION_BASE(SHARED_CACHED_DATA);
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return fw_addr;
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}
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static int
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pvr_riscv_vm_map(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj)
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{
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struct pvr_gem_object *pvr_obj = fw_obj->gem;
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return pvr_vm_map(pvr_dev->kernel_vm_ctx, pvr_obj, 0, fw_obj->fw_mm_node.start,
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pvr_gem_object_size(pvr_obj));
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}
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static void
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pvr_riscv_vm_unmap(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj)
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{
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struct pvr_gem_object *pvr_obj = fw_obj->gem;
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pvr_vm_unmap_obj(pvr_dev->kernel_vm_ctx, pvr_obj,
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fw_obj->fw_mm_node.start, fw_obj->fw_mm_node.size);
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}
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static bool
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pvr_riscv_irq_pending(struct pvr_device *pvr_dev)
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{
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return pvr_cr_read32(pvr_dev, ROGUE_CR_IRQ_OS0_EVENT_STATUS) &
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ROGUE_CR_IRQ_OS0_EVENT_STATUS_SOURCE_EN;
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}
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static void
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pvr_riscv_irq_clear(struct pvr_device *pvr_dev)
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{
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pvr_cr_write32(pvr_dev, ROGUE_CR_IRQ_OS0_EVENT_CLEAR,
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ROGUE_CR_IRQ_OS0_EVENT_CLEAR_SOURCE_EN);
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}
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const struct pvr_fw_defs pvr_fw_defs_riscv = {
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.init = pvr_riscv_init,
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.fw_process = pvr_riscv_fw_process,
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.vm_map = pvr_riscv_vm_map,
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.vm_unmap = pvr_riscv_vm_unmap,
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.get_fw_addr_with_offset = pvr_riscv_get_fw_addr_with_offset,
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.wrapper_init = pvr_riscv_wrapper_init,
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.irq_pending = pvr_riscv_irq_pending,
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.irq_clear = pvr_riscv_irq_clear,
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.has_fixed_data_addr = false,
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};
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@ -49,6 +49,14 @@ rogue_bif_init(struct pvr_device *pvr_dev)
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pvr_cr_write64(pvr_dev, BIF_CAT_BASEX(MMU_CONTEXT_MAPPING_FWPRIV),
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pc_addr);
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if (pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_RISCV) {
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pc_addr = (((u64)pc_dma_addr >> ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_ALIGNSHIFT)
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<< ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_SHIFT) &
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~ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_CLRMSK;
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pvr_cr_write64(pvr_dev, FWCORE_MEM_CAT_BASEX(MMU_CONTEXT_MAPPING_FWPRIV), pc_addr);
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}
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}
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static int
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@ -114,6 +122,9 @@ pvr_fw_start(struct pvr_device *pvr_dev)
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(void)pvr_cr_read32(pvr_dev, ROGUE_CR_SYS_BUS_SECURE); /* Fence write */
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}
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if (pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_RISCV)
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pvr_cr_write32(pvr_dev, ROGUE_CR_FWCORE_BOOT, 0);
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/* Set Rogue in soft-reset. */
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pvr_cr_write64(pvr_dev, ROGUE_CR_SOFT_RESET, soft_reset_mask);
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if (has_reset2)
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@ -167,6 +178,12 @@ pvr_fw_start(struct pvr_device *pvr_dev)
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/* ... and afterwards. */
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udelay(3);
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if (pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_RISCV) {
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/* Boot the FW. */
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pvr_cr_write32(pvr_dev, ROGUE_CR_FWCORE_BOOT, 1);
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udelay(3);
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}
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return 0;
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err_reset:
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41
drivers/gpu/drm/imagination/pvr_rogue_riscv.h
Normal file
41
drivers/gpu/drm/imagination/pvr_rogue_riscv.h
Normal file
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@ -0,0 +1,41 @@
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/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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/* Copyright (c) 2024 Imagination Technologies Ltd. */
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#ifndef PVR_ROGUE_RISCV_H
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#define PVR_ROGUE_RISCV_H
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#include "pvr_rogue_cr_defs.h"
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#include <linux/bitops.h>
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#include <linux/sizes.h>
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#include <linux/types.h>
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#define ROGUE_RISCVFW_REGION_SIZE SZ_256M
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#define ROGUE_RISCVFW_REGION_SHIFT __ffs(ROGUE_RISCVFW_REGION_SIZE)
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enum rogue_riscvfw_region {
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ROGUE_RISCV_REGION__RESERVED_0 = 0,
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ROGUE_RISCV_REGION__RESERVED_1,
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ROGUE_RISCV_REGION_SOCIF,
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ROGUE_RISCV_REGION__RESERVED_3,
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ROGUE_RISCV_REGION__RESERVED_4,
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ROGUE_RISCV_REGION_BOOTLDR_DATA,
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ROGUE_RISCV_REGION_SHARED_CACHED_DATA,
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ROGUE_RISCV_REGION__RESERVED_7,
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ROGUE_RISCV_REGION_COREMEM,
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ROGUE_RISCV_REGION__RESERVED_9,
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ROGUE_RISCV_REGION__RESERVED_A,
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ROGUE_RISCV_REGION__RESERVED_B,
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ROGUE_RISCV_REGION_BOOTLDR_CODE,
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ROGUE_RISCV_REGION_SHARED_UNCACHED_DATA,
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ROGUE_RISCV_REGION__RESERVED_E,
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ROGUE_RISCV_REGION__RESERVED_F,
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ROGUE_RISCV_REGION__COUNT,
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};
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#define ROGUE_RISCVFW_REGION_BASE(r) ((u32)(ROGUE_RISCV_REGION_##r) << ROGUE_RISCVFW_REGION_SHIFT)
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#define ROGUE_RISCVFW_REGION_REMAP_CR(r) \
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(ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0 + (u32)(ROGUE_RISCV_REGION_##r) * 8U)
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#endif /* PVR_ROGUE_RISCV_H */
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