forked from mirrors/linux
		
	mfd: rtsx: Remove LCTLR defination
To enable/disable ASPM we should find LINK CONTROL register in PCI config space. All old chip use 0x80 address, but new chip may use another address, so we using pci_find_capability() to get LINK CONTROL address. rtsx_gops.c was removed, we consider to put some common operations to this file, but the actual thing is, only a group of chips are in common ops1, and another group of chips in common ops2, it is hard to decide put which ops into generic ops file. Signed-off-by: Micky Ching <micky_ching@realsil.com.cn> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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					 6 changed files with 21 additions and 55 deletions
				
			
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			@ -13,7 +13,7 @@ obj-$(CONFIG_MFD_CROS_EC)	+= cros_ec.o
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obj-$(CONFIG_MFD_CROS_EC_I2C)	+= cros_ec_i2c.o
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obj-$(CONFIG_MFD_CROS_EC_SPI)	+= cros_ec_spi.o
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rtsx_pci-objs			:= rtsx_pcr.o rtsx_gops.o rts5209.o rts5229.o rtl8411.o rts5227.o rts5249.o
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rtsx_pci-objs			:= rtsx_pcr.o rts5209.o rts5229.o rtl8411.o rts5227.o rts5249.o
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obj-$(CONFIG_MFD_RTSX_PCI)	+= rtsx_pci.o
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obj-$(CONFIG_MFD_RTSX_USB)	+= rtsx_usb.o
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			@ -130,7 +130,7 @@ static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
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{
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	int err;
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	err = rtsx_gops_pm_reset(pcr);
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	err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
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	if (err < 0)
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		return err;
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			@ -119,7 +119,6 @@ static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
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		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
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	else
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		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
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	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00);
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	return rtsx_pci_send_cmd(pcr, 100);
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}
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			@ -128,7 +127,7 @@ static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
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{
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	int err;
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	err = rtsx_gops_pm_reset(pcr);
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	err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
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	if (err < 0)
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		return err;
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			@ -1,37 +0,0 @@
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/* Driver for Realtek PCI-Express card reader
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 *
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 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
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 *
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 * This program is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License as published by the
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 * Free Software Foundation; either version 2, or (at your option) any
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 * later version.
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 *
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 * This program is distributed in the hope that it will be useful, but
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 * WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License along
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 * with this program; if not, see <http://www.gnu.org/licenses/>.
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 *
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 * Author:
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 *   Micky Ching <micky_ching@realsil.com.cn>
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 */
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#include <linux/mfd/rtsx_pci.h>
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#include "rtsx_pcr.h"
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int rtsx_gops_pm_reset(struct rtsx_pcr *pcr)
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{
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	int err;
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	/* init aspm */
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	rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0x00);
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	err = rtsx_pci_update_cfg_byte(pcr, LCTLR, ~LCTLR_ASPM_CTL_MASK, 0x00);
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	if (err < 0)
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		return err;
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	/* reset PM_CTRL3 before send buffer cmd */
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	return rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
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}
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			@ -63,6 +63,18 @@ static const struct pci_device_id rtsx_pci_ids[] = {
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MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
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static inline void rtsx_pci_enable_aspm(struct rtsx_pcr *pcr)
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{
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	rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
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		0xFC, pcr->aspm_en);
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}
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static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr)
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{
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	rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
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		0xFC, 0);
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}
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void rtsx_pci_start_run(struct rtsx_pcr *pcr)
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{
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	/* If pci device removed, don't queue idle work any more */
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			@ -75,7 +87,7 @@ void rtsx_pci_start_run(struct rtsx_pcr *pcr)
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			pcr->ops->enable_auto_blink(pcr);
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		if (pcr->aspm_en)
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			rtsx_pci_write_config_byte(pcr, LCTLR, 0);
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			rtsx_pci_disable_aspm(pcr);
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	}
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	mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
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			@ -942,7 +954,7 @@ static void rtsx_pci_idle_work(struct work_struct *work)
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		pcr->ops->turn_off_led(pcr);
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	if (pcr->aspm_en)
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		rtsx_pci_write_config_byte(pcr, LCTLR, pcr->aspm_en);
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		rtsx_pci_enable_aspm(pcr);
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	mutex_unlock(&pcr->pcr_mutex);
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}
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			@ -968,6 +980,7 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
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{
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	int err;
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	pcr->pcie_cap = pci_find_capability(pcr->pci, PCI_CAP_ID_EXP);
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	rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
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	rtsx_pci_enable_bus_int(pcr);
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			@ -980,6 +993,7 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
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	/* Wait SSC power stable */
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	udelay(200);
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	rtsx_pci_disable_aspm(pcr);
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	if (pcr->ops->optimize_phy) {
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		err = pcr->ops->optimize_phy(pcr);
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		if (err < 0)
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			@ -1028,10 +1042,8 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
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	if (err < 0)
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		return err;
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	rtsx_pci_write_config_byte(pcr, LCTLR, 0);
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	/* Enable clk_request_n to enable clock power management */
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	rtsx_pci_write_config_byte(pcr, 0x81, 1);
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	rtsx_pci_write_config_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL + 1, 1);
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	/* Enter L1 when host tx idle */
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	rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
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			@ -716,15 +716,6 @@
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#define PHY_DUM_REG			0x1F
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#define LCTLR				0x80
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#define   LCTLR_EXT_SYNC		0x80
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#define   LCTLR_COMMON_CLOCK_CFG	0x40
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#define   LCTLR_RETRAIN_LINK		0x20
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#define   LCTLR_LINK_DISABLE		0x10
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#define   LCTLR_RCB			0x08
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#define   LCTLR_RESERVED		0x04
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#define   LCTLR_ASPM_CTL_MASK		0x03
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#define PCR_SETTING_REG1		0x724
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#define PCR_SETTING_REG2		0x814
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#define PCR_SETTING_REG3		0x747
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			@ -759,6 +750,7 @@ enum PDEV_STAT  {PDEV_STAT_IDLE, PDEV_STAT_RUN};
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struct rtsx_pcr {
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	struct pci_dev			*pci;
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	unsigned int			id;
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	int				pcie_cap;
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	/* pci resources */
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	unsigned long			addr;
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