forked from mirrors/linux
spi: Add Socionext F_OSPI SPI flash controller driver
Introduce Socionext F_OSPI controller driver. This controller is used to communicate with slave devices such as SPI Flash memories. It supports 4 slave devices and up to 8-bit wide bus, but supports master mode only. This driver uses spi-mem framework for SPI flash memory access, and can only operate indirect access mode and single data rate mode. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20221124003351.7792-3-hayashi.kunihiko@socionext.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Kunihiko Hayashi
Mark Brown
parent
41948bd9cf
commit
1b74dd64c8
3 changed files with 713 additions and 0 deletions
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@ -906,6 +906,15 @@ config SPI_SLAVE_MT27XX
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say Y or M here.If you are not sure, say N.
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SPI slave drivers for Mediatek MT27XX series ARM SoCs.
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config SPI_SN_F_OSPI
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tristate "Socionext F_OSPI SPI flash controller"
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depends on OF && HAS_IOMEM
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depends on SPI_MEM
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help
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This enables support for the Socionext F_OSPI controller
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for connecting an SPI Flash memory over up to 8-bit wide bus.
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It supports indirect access mode only.
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config SPI_SPRD
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tristate "Spreadtrum SPI controller"
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depends on ARCH_SPRD || COMPILE_TEST
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@ -121,6 +121,7 @@ obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o
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obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o
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obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o
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obj-$(CONFIG_SPI_SLAVE_MT27XX) += spi-slave-mt27xx.o
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obj-$(CONFIG_SPI_SN_F_OSPI) += spi-sn-f-ospi.o
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obj-$(CONFIG_SPI_SPRD) += spi-sprd.o
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obj-$(CONFIG_SPI_SPRD_ADI) += spi-sprd-adi.o
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obj-$(CONFIG_SPI_STM32) += spi-stm32.o
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703
drivers/spi/spi-sn-f-ospi.c
Normal file
703
drivers/spi/spi-sn-f-ospi.c
Normal file
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@ -0,0 +1,703 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Socionext SPI flash controller F_OSPI driver
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* Copyright (C) 2021 Socionext Inc.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi-mem.h>
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/* Registers */
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#define OSPI_PROT_CTL_INDIR 0x00
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#define OSPI_PROT_MODE_DATA_MASK GENMASK(31, 30)
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#define OSPI_PROT_MODE_ALT_MASK GENMASK(29, 28)
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#define OSPI_PROT_MODE_ADDR_MASK GENMASK(27, 26)
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#define OSPI_PROT_MODE_CODE_MASK GENMASK(25, 24)
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#define OSPI_PROT_MODE_SINGLE 0
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#define OSPI_PROT_MODE_DUAL 1
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#define OSPI_PROT_MODE_QUAD 2
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#define OSPI_PROT_MODE_OCTAL 3
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#define OSPI_PROT_DATA_RATE_DATA BIT(23)
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#define OSPI_PROT_DATA_RATE_ALT BIT(22)
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#define OSPI_PROT_DATA_RATE_ADDR BIT(21)
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#define OSPI_PROT_DATA_RATE_CODE BIT(20)
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#define OSPI_PROT_SDR 0
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#define OSPI_PROT_DDR 1
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#define OSPI_PROT_BIT_POS_DATA BIT(19)
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#define OSPI_PROT_BIT_POS_ALT BIT(18)
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#define OSPI_PROT_BIT_POS_ADDR BIT(17)
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#define OSPI_PROT_BIT_POS_CODE BIT(16)
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#define OSPI_PROT_SAMP_EDGE BIT(12)
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#define OSPI_PROT_DATA_UNIT_MASK GENMASK(11, 10)
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#define OSPI_PROT_DATA_UNIT_1B 0
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#define OSPI_PROT_DATA_UNIT_2B 1
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#define OSPI_PROT_DATA_UNIT_4B 3
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#define OSPI_PROT_TRANS_DIR_WRITE BIT(9)
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#define OSPI_PROT_DATA_EN BIT(8)
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#define OSPI_PROT_ALT_SIZE_MASK GENMASK(7, 5)
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#define OSPI_PROT_ADDR_SIZE_MASK GENMASK(4, 2)
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#define OSPI_PROT_CODE_SIZE_MASK GENMASK(1, 0)
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#define OSPI_CLK_CTL 0x10
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#define OSPI_CLK_CTL_BOOT_INT_CLK_EN BIT(16)
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#define OSPI_CLK_CTL_PHA BIT(12)
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#define OSPI_CLK_CTL_PHA_180 0
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#define OSPI_CLK_CTL_PHA_90 1
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#define OSPI_CLK_CTL_DIV GENMASK(9, 8)
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#define OSPI_CLK_CTL_DIV_1 0
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#define OSPI_CLK_CTL_DIV_2 1
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#define OSPI_CLK_CTL_DIV_4 2
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#define OSPI_CLK_CTL_DIV_8 3
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#define OSPI_CLK_CTL_INT_CLK_EN BIT(0)
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#define OSPI_CS_CTL1 0x14
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#define OSPI_CS_CTL2 0x18
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#define OSPI_SSEL 0x20
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#define OSPI_CMD_IDX_INDIR 0x40
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#define OSPI_ADDR 0x50
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#define OSPI_ALT_INDIR 0x60
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#define OSPI_DMY_INDIR 0x70
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#define OSPI_DAT 0x80
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#define OSPI_DAT_SWP_INDIR 0x90
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#define OSPI_DAT_SIZE_INDIR 0xA0
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#define OSPI_DAT_SIZE_EN BIT(15)
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#define OSPI_DAT_SIZE_MASK GENMASK(10, 0)
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#define OSPI_DAT_SIZE_MAX (OSPI_DAT_SIZE_MASK + 1)
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#define OSPI_TRANS_CTL 0xC0
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#define OSPI_TRANS_CTL_STOP_REQ BIT(1) /* RW1AC */
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#define OSPI_TRANS_CTL_START_REQ BIT(0) /* RW1AC */
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#define OSPI_ACC_MODE 0xC4
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#define OSPI_ACC_MODE_BOOT_DISABLE BIT(0)
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#define OSPI_SWRST 0xD0
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#define OSPI_SWRST_INDIR_WRITE_FIFO BIT(9) /* RW1AC */
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#define OSPI_SWRST_INDIR_READ_FIFO BIT(8) /* RW1AC */
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#define OSPI_STAT 0xE0
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#define OSPI_STAT_IS_AXI_WRITING BIT(10)
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#define OSPI_STAT_IS_AXI_READING BIT(9)
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#define OSPI_STAT_IS_SPI_INT_CLK_STOP BIT(4)
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#define OSPI_STAT_IS_SPI_IDLE BIT(3)
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#define OSPI_IRQ 0xF0
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#define OSPI_IRQ_CS_DEASSERT BIT(8)
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#define OSPI_IRQ_WRITE_BUF_READY BIT(2)
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#define OSPI_IRQ_READ_BUF_READY BIT(1)
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#define OSPI_IRQ_CS_TRANS_COMP BIT(0)
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#define OSPI_IRQ_ALL \
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(OSPI_IRQ_CS_DEASSERT | OSPI_IRQ_WRITE_BUF_READY \
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| OSPI_IRQ_READ_BUF_READY | OSPI_IRQ_CS_TRANS_COMP)
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#define OSPI_IRQ_STAT_EN 0xF4
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#define OSPI_IRQ_SIG_EN 0xF8
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/* Parameters */
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#define OSPI_NUM_CS 4
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#define OSPI_DUMMY_CYCLE_MAX 255
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#define OSPI_WAIT_MAX_MSEC 100
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struct f_ospi {
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void __iomem *base;
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struct device *dev;
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struct clk *clk;
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struct mutex mlock;
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};
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static u32 f_ospi_get_dummy_cycle(const struct spi_mem_op *op)
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{
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return (op->dummy.nbytes * 8) / op->dummy.buswidth;
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}
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static void f_ospi_clear_irq(struct f_ospi *ospi)
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{
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writel(OSPI_IRQ_CS_DEASSERT | OSPI_IRQ_CS_TRANS_COMP,
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ospi->base + OSPI_IRQ);
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}
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static void f_ospi_enable_irq_status(struct f_ospi *ospi, u32 irq_bits)
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{
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u32 val;
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val = readl(ospi->base + OSPI_IRQ_STAT_EN);
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val |= irq_bits;
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writel(val, ospi->base + OSPI_IRQ_STAT_EN);
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}
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static void f_ospi_disable_irq_status(struct f_ospi *ospi, u32 irq_bits)
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{
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u32 val;
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val = readl(ospi->base + OSPI_IRQ_STAT_EN);
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val &= ~irq_bits;
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writel(val, ospi->base + OSPI_IRQ_STAT_EN);
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}
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static void f_ospi_disable_irq_output(struct f_ospi *ospi, u32 irq_bits)
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{
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u32 val;
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val = readl(ospi->base + OSPI_IRQ_SIG_EN);
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val &= ~irq_bits;
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writel(val, ospi->base + OSPI_IRQ_SIG_EN);
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}
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static int f_ospi_prepare_config(struct f_ospi *ospi)
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{
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u32 val, stat0, stat1;
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/* G4: Disable internal clock */
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val = readl(ospi->base + OSPI_CLK_CTL);
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val &= ~(OSPI_CLK_CTL_BOOT_INT_CLK_EN | OSPI_CLK_CTL_INT_CLK_EN);
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writel(val, ospi->base + OSPI_CLK_CTL);
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/* G5: Wait for stop */
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stat0 = OSPI_STAT_IS_AXI_WRITING | OSPI_STAT_IS_AXI_READING;
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stat1 = OSPI_STAT_IS_SPI_IDLE | OSPI_STAT_IS_SPI_INT_CLK_STOP;
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return readl_poll_timeout(ospi->base + OSPI_STAT,
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val, (val & (stat0 | stat1)) == stat1,
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0, OSPI_WAIT_MAX_MSEC);
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}
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static int f_ospi_unprepare_config(struct f_ospi *ospi)
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{
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u32 val;
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/* G11: Enable internal clock */
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val = readl(ospi->base + OSPI_CLK_CTL);
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val |= OSPI_CLK_CTL_BOOT_INT_CLK_EN | OSPI_CLK_CTL_INT_CLK_EN;
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writel(val, ospi->base + OSPI_CLK_CTL);
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/* G12: Wait for clock to start */
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return readl_poll_timeout(ospi->base + OSPI_STAT,
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val, !(val & OSPI_STAT_IS_SPI_INT_CLK_STOP),
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0, OSPI_WAIT_MAX_MSEC);
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}
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static void f_ospi_config_clk(struct f_ospi *ospi, u32 device_hz)
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{
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long rate_hz = clk_get_rate(ospi->clk);
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u32 div = DIV_ROUND_UP(rate_hz, device_hz);
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u32 div_reg;
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u32 val;
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if (rate_hz < device_hz) {
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dev_warn(ospi->dev, "Device frequency too large: %d\n",
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device_hz);
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div_reg = OSPI_CLK_CTL_DIV_1;
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} else {
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if (div == 1) {
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div_reg = OSPI_CLK_CTL_DIV_1;
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} else if (div == 2) {
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div_reg = OSPI_CLK_CTL_DIV_2;
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} else if (div <= 4) {
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div_reg = OSPI_CLK_CTL_DIV_4;
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} else if (div <= 8) {
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div_reg = OSPI_CLK_CTL_DIV_8;
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} else {
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dev_warn(ospi->dev, "Device frequency too small: %d\n",
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device_hz);
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div_reg = OSPI_CLK_CTL_DIV_8;
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}
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}
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/*
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* G7: Set clock mode
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* clock phase is fixed at 180 degrees and configure edge direction
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* instead.
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*/
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val = readl(ospi->base + OSPI_CLK_CTL);
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val &= ~(OSPI_CLK_CTL_PHA | OSPI_CLK_CTL_DIV);
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val |= FIELD_PREP(OSPI_CLK_CTL_PHA, OSPI_CLK_CTL_PHA_180)
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| FIELD_PREP(OSPI_CLK_CTL_DIV, div_reg);
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writel(val, ospi->base + OSPI_CLK_CTL);
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}
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static void f_ospi_config_dll(struct f_ospi *ospi)
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{
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/* G8: Configure DLL, nothing */
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}
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static u8 f_ospi_get_mode(struct f_ospi *ospi, int width, int data_size)
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{
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u8 mode = OSPI_PROT_MODE_SINGLE;
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switch (width) {
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case 1:
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mode = OSPI_PROT_MODE_SINGLE;
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break;
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case 2:
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mode = OSPI_PROT_MODE_DUAL;
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break;
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case 4:
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mode = OSPI_PROT_MODE_QUAD;
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break;
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case 8:
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mode = OSPI_PROT_MODE_OCTAL;
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break;
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default:
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if (data_size)
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dev_err(ospi->dev, "Invalid buswidth: %d\n", width);
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break;
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}
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return mode;
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}
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static void f_ospi_config_indir_protocol(struct f_ospi *ospi,
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struct spi_mem *mem,
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const struct spi_mem_op *op)
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{
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struct spi_device *spi = mem->spi;
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u8 mode;
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u32 prot = 0, val;
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int unit;
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/* Set one chip select */
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writel(BIT(spi->chip_select), ospi->base + OSPI_SSEL);
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mode = f_ospi_get_mode(ospi, op->cmd.buswidth, 1);
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prot |= FIELD_PREP(OSPI_PROT_MODE_CODE_MASK, mode);
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mode = f_ospi_get_mode(ospi, op->addr.buswidth, op->addr.nbytes);
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prot |= FIELD_PREP(OSPI_PROT_MODE_ADDR_MASK, mode);
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mode = f_ospi_get_mode(ospi, op->data.buswidth, op->data.nbytes);
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prot |= FIELD_PREP(OSPI_PROT_MODE_DATA_MASK, mode);
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prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_DATA, OSPI_PROT_SDR);
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prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_ALT, OSPI_PROT_SDR);
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prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_ADDR, OSPI_PROT_SDR);
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prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_CODE, OSPI_PROT_SDR);
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if (spi->mode & SPI_LSB_FIRST)
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prot |= OSPI_PROT_BIT_POS_DATA | OSPI_PROT_BIT_POS_ALT
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| OSPI_PROT_BIT_POS_ADDR | OSPI_PROT_BIT_POS_CODE;
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if (spi->mode & SPI_CPHA)
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prot |= OSPI_PROT_SAMP_EDGE;
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/* Examine nbytes % 4 */
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switch (op->data.nbytes & 0x3) {
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case 0:
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unit = OSPI_PROT_DATA_UNIT_4B;
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val = 0;
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break;
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case 2:
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unit = OSPI_PROT_DATA_UNIT_2B;
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val = OSPI_DAT_SIZE_EN | (op->data.nbytes - 1);
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break;
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default:
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unit = OSPI_PROT_DATA_UNIT_1B;
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val = OSPI_DAT_SIZE_EN | (op->data.nbytes - 1);
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break;
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}
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prot |= FIELD_PREP(OSPI_PROT_DATA_UNIT_MASK, unit);
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switch (op->data.dir) {
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case SPI_MEM_DATA_IN:
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prot |= OSPI_PROT_DATA_EN;
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break;
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case SPI_MEM_DATA_OUT:
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prot |= OSPI_PROT_TRANS_DIR_WRITE | OSPI_PROT_DATA_EN;
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break;
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case SPI_MEM_NO_DATA:
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prot |= OSPI_PROT_TRANS_DIR_WRITE;
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break;
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default:
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dev_warn(ospi->dev, "Unsupported direction");
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break;
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}
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prot |= FIELD_PREP(OSPI_PROT_ADDR_SIZE_MASK, op->addr.nbytes);
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prot |= FIELD_PREP(OSPI_PROT_CODE_SIZE_MASK, 1); /* 1byte */
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writel(prot, ospi->base + OSPI_PROT_CTL_INDIR);
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writel(val, ospi->base + OSPI_DAT_SIZE_INDIR);
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}
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static int f_ospi_indir_prepare_op(struct f_ospi *ospi, struct spi_mem *mem,
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const struct spi_mem_op *op)
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{
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struct spi_device *spi = mem->spi;
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u32 irq_stat_en;
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int ret;
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ret = f_ospi_prepare_config(ospi);
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if (ret)
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return ret;
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f_ospi_config_clk(ospi, spi->max_speed_hz);
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f_ospi_config_indir_protocol(ospi, mem, op);
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writel(f_ospi_get_dummy_cycle(op), ospi->base + OSPI_DMY_INDIR);
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writel(op->addr.val, ospi->base + OSPI_ADDR);
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writel(op->cmd.opcode, ospi->base + OSPI_CMD_IDX_INDIR);
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f_ospi_clear_irq(ospi);
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switch (op->data.dir) {
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case SPI_MEM_DATA_IN:
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irq_stat_en = OSPI_IRQ_READ_BUF_READY | OSPI_IRQ_CS_TRANS_COMP;
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break;
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case SPI_MEM_DATA_OUT:
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irq_stat_en = OSPI_IRQ_WRITE_BUF_READY | OSPI_IRQ_CS_TRANS_COMP;
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break;
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case SPI_MEM_NO_DATA:
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irq_stat_en = OSPI_IRQ_CS_TRANS_COMP;
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break;
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default:
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dev_warn(ospi->dev, "Unsupported direction");
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irq_stat_en = 0;
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}
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f_ospi_disable_irq_status(ospi, ~irq_stat_en);
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f_ospi_enable_irq_status(ospi, irq_stat_en);
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return f_ospi_unprepare_config(ospi);
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}
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static void f_ospi_indir_start_xfer(struct f_ospi *ospi)
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{
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/* Write only 1, auto cleared */
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writel(OSPI_TRANS_CTL_START_REQ, ospi->base + OSPI_TRANS_CTL);
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}
|
||||
|
||||
static void f_ospi_indir_stop_xfer(struct f_ospi *ospi)
|
||||
{
|
||||
/* Write only 1, auto cleared */
|
||||
writel(OSPI_TRANS_CTL_STOP_REQ, ospi->base + OSPI_TRANS_CTL);
|
||||
}
|
||||
|
||||
static int f_ospi_indir_wait_xfer_complete(struct f_ospi *ospi)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
return readl_poll_timeout(ospi->base + OSPI_IRQ, val,
|
||||
val & OSPI_IRQ_CS_TRANS_COMP,
|
||||
0, OSPI_WAIT_MAX_MSEC);
|
||||
}
|
||||
|
||||
static int f_ospi_indir_read(struct f_ospi *ospi, struct spi_mem *mem,
|
||||
const struct spi_mem_op *op)
|
||||
{
|
||||
u8 *buf = op->data.buf.in;
|
||||
u32 val;
|
||||
int i, ret;
|
||||
|
||||
mutex_lock(&ospi->mlock);
|
||||
|
||||
/* E1-2: Prepare transfer operation */
|
||||
ret = f_ospi_indir_prepare_op(ospi, mem, op);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
f_ospi_indir_start_xfer(ospi);
|
||||
|
||||
/* E3-4: Wait for ready and read data */
|
||||
for (i = 0; i < op->data.nbytes; i++) {
|
||||
ret = readl_poll_timeout(ospi->base + OSPI_IRQ, val,
|
||||
val & OSPI_IRQ_READ_BUF_READY,
|
||||
0, OSPI_WAIT_MAX_MSEC);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
buf[i] = readl(ospi->base + OSPI_DAT) & 0xFF;
|
||||
}
|
||||
|
||||
/* E5-6: Stop transfer if data size is nothing */
|
||||
if (!(readl(ospi->base + OSPI_DAT_SIZE_INDIR) & OSPI_DAT_SIZE_EN))
|
||||
f_ospi_indir_stop_xfer(ospi);
|
||||
|
||||
/* E7-8: Wait for completion and clear */
|
||||
ret = f_ospi_indir_wait_xfer_complete(ospi);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
writel(OSPI_IRQ_CS_TRANS_COMP, ospi->base + OSPI_IRQ);
|
||||
|
||||
/* E9: Do nothing if data size is valid */
|
||||
if (readl(ospi->base + OSPI_DAT_SIZE_INDIR) & OSPI_DAT_SIZE_EN)
|
||||
goto out;
|
||||
|
||||
/* E10-11: Reset and check read fifo */
|
||||
writel(OSPI_SWRST_INDIR_READ_FIFO, ospi->base + OSPI_SWRST);
|
||||
|
||||
ret = readl_poll_timeout(ospi->base + OSPI_SWRST, val,
|
||||
!(val & OSPI_SWRST_INDIR_READ_FIFO),
|
||||
0, OSPI_WAIT_MAX_MSEC);
|
||||
out:
|
||||
mutex_unlock(&ospi->mlock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int f_ospi_indir_write(struct f_ospi *ospi, struct spi_mem *mem,
|
||||
const struct spi_mem_op *op)
|
||||
{
|
||||
u8 *buf = (u8 *)op->data.buf.out;
|
||||
u32 val;
|
||||
int i, ret;
|
||||
|
||||
mutex_lock(&ospi->mlock);
|
||||
|
||||
/* F1-3: Prepare transfer operation */
|
||||
ret = f_ospi_indir_prepare_op(ospi, mem, op);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
f_ospi_indir_start_xfer(ospi);
|
||||
|
||||
if (!(readl(ospi->base + OSPI_PROT_CTL_INDIR) & OSPI_PROT_DATA_EN))
|
||||
goto nodata;
|
||||
|
||||
/* F4-5: Wait for buffer ready and write data */
|
||||
for (i = 0; i < op->data.nbytes; i++) {
|
||||
ret = readl_poll_timeout(ospi->base + OSPI_IRQ, val,
|
||||
val & OSPI_IRQ_WRITE_BUF_READY,
|
||||
0, OSPI_WAIT_MAX_MSEC);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
writel(buf[i], ospi->base + OSPI_DAT);
|
||||
}
|
||||
|
||||
/* F6-7: Stop transfer if data size is nothing */
|
||||
if (!(readl(ospi->base + OSPI_DAT_SIZE_INDIR) & OSPI_DAT_SIZE_EN))
|
||||
f_ospi_indir_stop_xfer(ospi);
|
||||
|
||||
nodata:
|
||||
/* F8-9: Wait for completion and clear */
|
||||
ret = f_ospi_indir_wait_xfer_complete(ospi);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
writel(OSPI_IRQ_CS_TRANS_COMP, ospi->base + OSPI_IRQ);
|
||||
out:
|
||||
mutex_unlock(&ospi->mlock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int f_ospi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
|
||||
{
|
||||
struct f_ospi *ospi = spi_controller_get_devdata(mem->spi->master);
|
||||
int err = 0;
|
||||
|
||||
switch (op->data.dir) {
|
||||
case SPI_MEM_DATA_IN:
|
||||
err = f_ospi_indir_read(ospi, mem, op);
|
||||
break;
|
||||
|
||||
case SPI_MEM_DATA_OUT:
|
||||
fallthrough;
|
||||
case SPI_MEM_NO_DATA:
|
||||
err = f_ospi_indir_write(ospi, mem, op);
|
||||
break;
|
||||
|
||||
default:
|
||||
dev_warn(ospi->dev, "Unsupported direction");
|
||||
err = -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static bool f_ospi_supports_op_width(struct spi_mem *mem,
|
||||
const struct spi_mem_op *op)
|
||||
{
|
||||
u8 width_available[] = { 0, 1, 2, 4, 8 };
|
||||
u8 width_op[] = { op->cmd.buswidth, op->addr.buswidth,
|
||||
op->dummy.buswidth, op->data.buswidth };
|
||||
bool is_match_found;
|
||||
int i, j;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(width_op); i++) {
|
||||
is_match_found = false;
|
||||
|
||||
for (j = 0; j < ARRAY_SIZE(width_available); j++) {
|
||||
if (width_op[i] == width_available[j]) {
|
||||
is_match_found = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!is_match_found)
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool f_ospi_supports_op(struct spi_mem *mem,
|
||||
const struct spi_mem_op *op)
|
||||
{
|
||||
if (f_ospi_get_dummy_cycle(op) > OSPI_DUMMY_CYCLE_MAX)
|
||||
return false;
|
||||
|
||||
if (op->addr.nbytes > 4)
|
||||
return false;
|
||||
|
||||
if (!f_ospi_supports_op_width(mem, op))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static int f_ospi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
|
||||
{
|
||||
op->data.nbytes = min((int)op->data.nbytes, (int)(OSPI_DAT_SIZE_MAX));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct spi_controller_mem_ops f_ospi_mem_ops = {
|
||||
.adjust_op_size = f_ospi_adjust_op_size,
|
||||
.supports_op = f_ospi_supports_op,
|
||||
.exec_op = f_ospi_exec_op,
|
||||
};
|
||||
|
||||
static int f_ospi_init(struct f_ospi *ospi)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = f_ospi_prepare_config(ospi);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Disable boot signal */
|
||||
writel(OSPI_ACC_MODE_BOOT_DISABLE, ospi->base + OSPI_ACC_MODE);
|
||||
|
||||
f_ospi_config_dll(ospi);
|
||||
|
||||
/* Disable IRQ */
|
||||
f_ospi_clear_irq(ospi);
|
||||
f_ospi_disable_irq_status(ospi, OSPI_IRQ_ALL);
|
||||
f_ospi_disable_irq_output(ospi, OSPI_IRQ_ALL);
|
||||
|
||||
return f_ospi_unprepare_config(ospi);
|
||||
}
|
||||
|
||||
static int f_ospi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_controller *ctlr;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct f_ospi *ospi;
|
||||
u32 num_cs = OSPI_NUM_CS;
|
||||
int ret;
|
||||
|
||||
ctlr = spi_alloc_master(dev, sizeof(*ospi));
|
||||
if (!ctlr)
|
||||
return -ENOMEM;
|
||||
|
||||
ctlr->mode_bits = SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL
|
||||
| SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_OCTAL
|
||||
| SPI_MODE_0 | SPI_MODE_1 | SPI_LSB_FIRST;
|
||||
ctlr->mem_ops = &f_ospi_mem_ops;
|
||||
ctlr->bus_num = -1;
|
||||
of_property_read_u32(dev->of_node, "num-cs", &num_cs);
|
||||
if (num_cs > OSPI_NUM_CS) {
|
||||
dev_err(dev, "num-cs too large: %d\n", num_cs);
|
||||
return -ENOMEM;
|
||||
}
|
||||
ctlr->num_chipselect = num_cs;
|
||||
ctlr->dev.of_node = dev->of_node;
|
||||
|
||||
ospi = spi_controller_get_devdata(ctlr);
|
||||
ospi->dev = dev;
|
||||
|
||||
platform_set_drvdata(pdev, ospi);
|
||||
|
||||
ospi->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(ospi->base)) {
|
||||
ret = PTR_ERR(ospi->base);
|
||||
goto err_put_ctlr;
|
||||
}
|
||||
|
||||
ospi->clk = devm_clk_get(dev, NULL);
|
||||
if (IS_ERR(ospi->clk)) {
|
||||
ret = PTR_ERR(ospi->clk);
|
||||
goto err_put_ctlr;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(ospi->clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to enable the clock\n");
|
||||
goto err_disable_clk;
|
||||
}
|
||||
|
||||
mutex_init(&ospi->mlock);
|
||||
|
||||
ret = f_ospi_init(ospi);
|
||||
if (ret)
|
||||
goto err_destroy_mutex;
|
||||
|
||||
ret = devm_spi_register_controller(dev, ctlr);
|
||||
if (ret)
|
||||
goto err_destroy_mutex;
|
||||
|
||||
return 0;
|
||||
|
||||
err_destroy_mutex:
|
||||
mutex_destroy(&ospi->mlock);
|
||||
|
||||
err_disable_clk:
|
||||
clk_disable_unprepare(ospi->clk);
|
||||
|
||||
err_put_ctlr:
|
||||
spi_controller_put(ctlr);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int f_ospi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct f_ospi *ospi = platform_get_drvdata(pdev);
|
||||
|
||||
clk_disable_unprepare(ospi->clk);
|
||||
|
||||
mutex_destroy(&ospi->mlock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id f_ospi_dt_ids[] = {
|
||||
{ .compatible = "socionext,f-ospi" },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, f_ospi_dt_ids);
|
||||
|
||||
static struct platform_driver f_ospi_driver = {
|
||||
.driver = {
|
||||
.name = "socionext,f-ospi",
|
||||
.of_match_table = f_ospi_dt_ids,
|
||||
},
|
||||
.probe = f_ospi_probe,
|
||||
.remove = f_ospi_remove,
|
||||
};
|
||||
module_platform_driver(f_ospi_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Socionext F_OSPI controller driver");
|
||||
MODULE_AUTHOR("Socionext Inc.");
|
||||
MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in a new issue