forked from mirrors/linux
usb: cdns3: add NXP imx8qm glue layer
There is a Cadence USB3 core for imx8qm and imx8qxp SoCs, the cdns core is the child for this glue layer device. Signed-off-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Felipe Balbi <balbi@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Peter Chen
Greg Kroah-Hartman
parent
09ed259fac
commit
1e056efab9
3 changed files with 227 additions and 0 deletions
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@ -53,4 +53,14 @@ config USB_CDNS3_TI
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e.g. J721e.
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config USB_CDNS3_IMX
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tristate "Cadence USB3 support on NXP i.MX platforms"
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depends on ARCH_MXC || COMPILE_TEST
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default USB_CDNS3
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help
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Say 'Y' or 'M' here if you are building for NXP i.MX
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platforms that contain Cadence USB3 controller core.
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For example, imx8qm and imx8qxp.
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endif
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@ -15,3 +15,4 @@ cdns3-$(CONFIG_USB_CDNS3_HOST) += host.o
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obj-$(CONFIG_USB_CDNS3_PCI_WRAP) += cdns3-pci-wrap.o
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obj-$(CONFIG_USB_CDNS3_TI) += cdns3-ti.o
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obj-$(CONFIG_USB_CDNS3_IMX) += cdns3-imx.o
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216
drivers/usb/cdns3/cdns3-imx.c
Normal file
216
drivers/usb/cdns3/cdns3-imx.c
Normal file
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@ -0,0 +1,216 @@
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// SPDX-License-Identifier: GPL-2.0
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/**
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* cdns3-imx.c - NXP i.MX specific Glue layer for Cadence USB Controller
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*
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* Copyright (C) 2019 NXP
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*/
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include <linux/of_platform.h>
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#include <linux/iopoll.h>
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#define USB3_CORE_CTRL1 0x00
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#define USB3_CORE_CTRL2 0x04
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#define USB3_INT_REG 0x08
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#define USB3_CORE_STATUS 0x0c
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#define XHCI_DEBUG_LINK_ST 0x10
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#define XHCI_DEBUG_BUS 0x14
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#define USB3_SSPHY_CTRL1 0x40
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#define USB3_SSPHY_CTRL2 0x44
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#define USB3_SSPHY_STATUS 0x4c
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#define USB2_PHY_CTRL1 0x50
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#define USB2_PHY_CTRL2 0x54
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#define USB2_PHY_STATUS 0x5c
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/* Register bits definition */
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/* USB3_CORE_CTRL1 */
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#define SW_RESET_MASK (0x3f << 26)
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#define PWR_SW_RESET BIT(31)
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#define APB_SW_RESET BIT(30)
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#define AXI_SW_RESET BIT(29)
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#define RW_SW_RESET BIT(28)
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#define PHY_SW_RESET BIT(27)
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#define PHYAHB_SW_RESET BIT(26)
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#define ALL_SW_RESET (PWR_SW_RESET | APB_SW_RESET | AXI_SW_RESET | \
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RW_SW_RESET | PHY_SW_RESET | PHYAHB_SW_RESET)
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#define OC_DISABLE BIT(9)
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#define MDCTRL_CLK_SEL BIT(7)
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#define MODE_STRAP_MASK (0x7)
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#define DEV_MODE (1 << 2)
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#define HOST_MODE (1 << 1)
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#define OTG_MODE (1 << 0)
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/* USB3_INT_REG */
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#define CLK_125_REQ BIT(29)
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#define LPM_CLK_REQ BIT(28)
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#define DEVU3_WAEKUP_EN BIT(14)
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#define OTG_WAKEUP_EN BIT(12)
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#define DEV_INT_EN (3 << 8) /* DEV INT b9:8 */
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#define HOST_INT1_EN (1 << 0) /* HOST INT b7:0 */
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/* USB3_CORE_STATUS */
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#define MDCTRL_CLK_STATUS BIT(15)
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#define DEV_POWER_ON_READY BIT(13)
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#define HOST_POWER_ON_READY BIT(12)
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/* USB3_SSPHY_STATUS */
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#define CLK_VALID_MASK (0x3f << 26)
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#define CLK_VALID_COMPARE_BITS (0xf << 28)
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#define PHY_REFCLK_REQ (1 << 0)
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struct cdns_imx {
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struct device *dev;
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void __iomem *noncore;
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struct clk_bulk_data *clks;
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int num_clks;
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};
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static inline u32 cdns_imx_readl(struct cdns_imx *data, u32 offset)
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{
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return readl(data->noncore + offset);
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}
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static inline void cdns_imx_writel(struct cdns_imx *data, u32 offset, u32 value)
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{
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writel(value, data->noncore + offset);
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}
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static const struct clk_bulk_data imx_cdns3_core_clks[] = {
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{ .id = "usb3_lpm_clk" },
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{ .id = "usb3_bus_clk" },
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{ .id = "usb3_aclk" },
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{ .id = "usb3_ipg_clk" },
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{ .id = "usb3_core_pclk" },
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};
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static int cdns_imx_noncore_init(struct cdns_imx *data)
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{
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u32 value;
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int ret;
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struct device *dev = data->dev;
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cdns_imx_writel(data, USB3_SSPHY_STATUS, CLK_VALID_MASK);
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udelay(1);
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ret = readl_poll_timeout(data->noncore + USB3_SSPHY_STATUS, value,
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(value & CLK_VALID_COMPARE_BITS) == CLK_VALID_COMPARE_BITS,
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10, 100000);
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if (ret) {
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dev_err(dev, "wait clkvld timeout\n");
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return ret;
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}
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value = cdns_imx_readl(data, USB3_CORE_CTRL1);
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value |= ALL_SW_RESET;
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cdns_imx_writel(data, USB3_CORE_CTRL1, value);
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udelay(1);
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value = cdns_imx_readl(data, USB3_CORE_CTRL1);
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value = (value & ~MODE_STRAP_MASK) | OTG_MODE | OC_DISABLE;
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cdns_imx_writel(data, USB3_CORE_CTRL1, value);
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value = cdns_imx_readl(data, USB3_INT_REG);
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value |= HOST_INT1_EN | DEV_INT_EN;
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cdns_imx_writel(data, USB3_INT_REG, value);
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value = cdns_imx_readl(data, USB3_CORE_CTRL1);
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value &= ~ALL_SW_RESET;
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cdns_imx_writel(data, USB3_CORE_CTRL1, value);
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return ret;
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}
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static int cdns_imx_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *node = dev->of_node;
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struct cdns_imx *data;
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int ret;
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if (!node)
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return -ENODEV;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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platform_set_drvdata(pdev, data);
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data->dev = dev;
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data->noncore = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(data->noncore)) {
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dev_err(dev, "can't map IOMEM resource\n");
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return PTR_ERR(data->noncore);
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}
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data->num_clks = ARRAY_SIZE(imx_cdns3_core_clks);
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data->clks = (struct clk_bulk_data *)imx_cdns3_core_clks;
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ret = devm_clk_bulk_get(dev, data->num_clks, data->clks);
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if (ret)
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return ret;
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ret = clk_bulk_prepare_enable(data->num_clks, data->clks);
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if (ret)
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return ret;
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ret = cdns_imx_noncore_init(data);
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if (ret)
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goto err;
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ret = of_platform_populate(node, NULL, NULL, dev);
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if (ret) {
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dev_err(dev, "failed to create children: %d\n", ret);
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goto err;
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}
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return ret;
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err:
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clk_bulk_disable_unprepare(data->num_clks, data->clks);
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return ret;
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}
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static int cdns_imx_remove_core(struct device *dev, void *data)
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{
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struct platform_device *pdev = to_platform_device(dev);
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platform_device_unregister(pdev);
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return 0;
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}
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static int cdns_imx_remove(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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device_for_each_child(dev, NULL, cdns_imx_remove_core);
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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static const struct of_device_id cdns_imx_of_match[] = {
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{ .compatible = "fsl,imx8qm-usb3", },
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{},
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};
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MODULE_DEVICE_TABLE(of, cdns_imx_of_match);
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static struct platform_driver cdns_imx_driver = {
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.probe = cdns_imx_probe,
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.remove = cdns_imx_remove,
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.driver = {
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.name = "cdns3-imx",
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.of_match_table = cdns_imx_of_match,
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},
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};
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module_platform_driver(cdns_imx_driver);
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MODULE_ALIAS("platform:cdns3-imx");
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MODULE_AUTHOR("Peter Chen <peter.chen@nxp.com>");
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Cadence USB3 i.MX Glue Layer");
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