forked from mirrors/linux
arm64: KVM: Move away from the assembly version of the world switch
This is it. We remove all of the code that has now been rewritten. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
This commit is contained in:
Marc Zyngier
parent
910917bb7d
commit
1ea66d27e7
4 changed files with 1 additions and 1485 deletions
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@ -23,8 +23,6 @@ kvm-$(CONFIG_KVM_ARM_HOST) += guest.o debug.o reset.o sys_regs.o sys_regs_generi
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kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic.o
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kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic-v2.o
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kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic-v2-emul.o
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kvm-$(CONFIG_KVM_ARM_HOST) += vgic-v2-switch.o
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kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic-v3.o
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kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic-v3-emul.o
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kvm-$(CONFIG_KVM_ARM_HOST) += vgic-v3-switch.o
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kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/arch_timer.o
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1081
arch/arm64/kvm/hyp.S
1081
arch/arm64/kvm/hyp.S
File diff suppressed because it is too large
Load diff
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@ -1,134 +0,0 @@
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/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/linkage.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/assembler.h>
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#include <asm/memory.h>
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#include <asm/asm-offsets.h>
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#include <asm/kvm.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_mmu.h>
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.text
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.pushsection .hyp.text, "ax"
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/*
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* Save the VGIC CPU state into memory
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* x0: Register pointing to VCPU struct
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* Do not corrupt x1!!!
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*/
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ENTRY(__save_vgic_v2_state)
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__save_vgic_v2_state:
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/* Get VGIC VCTRL base into x2 */
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ldr x2, [x0, #VCPU_KVM]
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kern_hyp_va x2
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ldr x2, [x2, #KVM_VGIC_VCTRL]
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kern_hyp_va x2
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cbz x2, 2f // disabled
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/* Compute the address of struct vgic_cpu */
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add x3, x0, #VCPU_VGIC_CPU
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/* Save all interesting registers */
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ldr w5, [x2, #GICH_VMCR]
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ldr w6, [x2, #GICH_MISR]
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ldr w7, [x2, #GICH_EISR0]
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ldr w8, [x2, #GICH_EISR1]
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ldr w9, [x2, #GICH_ELRSR0]
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ldr w10, [x2, #GICH_ELRSR1]
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ldr w11, [x2, #GICH_APR]
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CPU_BE( rev w5, w5 )
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CPU_BE( rev w6, w6 )
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CPU_BE( rev w7, w7 )
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CPU_BE( rev w8, w8 )
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CPU_BE( rev w9, w9 )
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CPU_BE( rev w10, w10 )
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CPU_BE( rev w11, w11 )
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str w5, [x3, #VGIC_V2_CPU_VMCR]
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str w6, [x3, #VGIC_V2_CPU_MISR]
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CPU_LE( str w7, [x3, #VGIC_V2_CPU_EISR] )
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CPU_LE( str w8, [x3, #(VGIC_V2_CPU_EISR + 4)] )
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CPU_LE( str w9, [x3, #VGIC_V2_CPU_ELRSR] )
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CPU_LE( str w10, [x3, #(VGIC_V2_CPU_ELRSR + 4)] )
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CPU_BE( str w7, [x3, #(VGIC_V2_CPU_EISR + 4)] )
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CPU_BE( str w8, [x3, #VGIC_V2_CPU_EISR] )
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CPU_BE( str w9, [x3, #(VGIC_V2_CPU_ELRSR + 4)] )
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CPU_BE( str w10, [x3, #VGIC_V2_CPU_ELRSR] )
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str w11, [x3, #VGIC_V2_CPU_APR]
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/* Clear GICH_HCR */
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str wzr, [x2, #GICH_HCR]
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/* Save list registers */
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add x2, x2, #GICH_LR0
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ldr w4, [x3, #VGIC_CPU_NR_LR]
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add x3, x3, #VGIC_V2_CPU_LR
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1: ldr w5, [x2], #4
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CPU_BE( rev w5, w5 )
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str w5, [x3], #4
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sub w4, w4, #1
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cbnz w4, 1b
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2:
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ret
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ENDPROC(__save_vgic_v2_state)
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/*
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* Restore the VGIC CPU state from memory
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* x0: Register pointing to VCPU struct
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*/
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ENTRY(__restore_vgic_v2_state)
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__restore_vgic_v2_state:
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/* Get VGIC VCTRL base into x2 */
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ldr x2, [x0, #VCPU_KVM]
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kern_hyp_va x2
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ldr x2, [x2, #KVM_VGIC_VCTRL]
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kern_hyp_va x2
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cbz x2, 2f // disabled
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/* Compute the address of struct vgic_cpu */
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add x3, x0, #VCPU_VGIC_CPU
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/* We only restore a minimal set of registers */
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ldr w4, [x3, #VGIC_V2_CPU_HCR]
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ldr w5, [x3, #VGIC_V2_CPU_VMCR]
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ldr w6, [x3, #VGIC_V2_CPU_APR]
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CPU_BE( rev w4, w4 )
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CPU_BE( rev w5, w5 )
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CPU_BE( rev w6, w6 )
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str w4, [x2, #GICH_HCR]
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str w5, [x2, #GICH_VMCR]
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str w6, [x2, #GICH_APR]
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/* Restore list registers */
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add x2, x2, #GICH_LR0
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ldr w4, [x3, #VGIC_CPU_NR_LR]
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add x3, x3, #VGIC_V2_CPU_LR
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1: ldr w5, [x3], #4
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CPU_BE( rev w5, w5 )
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str w5, [x2], #4
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sub w4, w4, #1
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cbnz w4, 1b
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2:
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ret
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ENDPROC(__restore_vgic_v2_state)
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.popsection
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@ -1,269 +0,0 @@
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/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/linkage.h>
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#include <linux/irqchip/arm-gic-v3.h>
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#include <asm/assembler.h>
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#include <asm/memory.h>
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#include <asm/asm-offsets.h>
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#include <asm/kvm.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_arm.h>
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.text
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.pushsection .hyp.text, "ax"
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/*
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* We store LRs in reverse order to let the CPU deal with streaming
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* access. Use this macro to make it look saner...
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*/
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#define LR_OFFSET(n) (VGIC_V3_CPU_LR + (15 - n) * 8)
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/*
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* Save the VGIC CPU state into memory
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* x0: Register pointing to VCPU struct
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* Do not corrupt x1!!!
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*/
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.macro save_vgic_v3_state
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// Compute the address of struct vgic_cpu
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add x3, x0, #VCPU_VGIC_CPU
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// Make sure stores to the GIC via the memory mapped interface
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// are now visible to the system register interface
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dsb st
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// Save all interesting registers
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mrs_s x5, ICH_VMCR_EL2
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mrs_s x6, ICH_MISR_EL2
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mrs_s x7, ICH_EISR_EL2
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mrs_s x8, ICH_ELSR_EL2
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str w5, [x3, #VGIC_V3_CPU_VMCR]
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str w6, [x3, #VGIC_V3_CPU_MISR]
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str w7, [x3, #VGIC_V3_CPU_EISR]
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str w8, [x3, #VGIC_V3_CPU_ELRSR]
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msr_s ICH_HCR_EL2, xzr
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mrs_s x21, ICH_VTR_EL2
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mvn w22, w21
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ubfiz w23, w22, 2, 4 // w23 = (15 - ListRegs) * 4
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adr x24, 1f
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add x24, x24, x23
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br x24
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1:
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mrs_s x20, ICH_LR15_EL2
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mrs_s x19, ICH_LR14_EL2
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mrs_s x18, ICH_LR13_EL2
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mrs_s x17, ICH_LR12_EL2
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mrs_s x16, ICH_LR11_EL2
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mrs_s x15, ICH_LR10_EL2
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mrs_s x14, ICH_LR9_EL2
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mrs_s x13, ICH_LR8_EL2
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mrs_s x12, ICH_LR7_EL2
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mrs_s x11, ICH_LR6_EL2
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mrs_s x10, ICH_LR5_EL2
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mrs_s x9, ICH_LR4_EL2
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mrs_s x8, ICH_LR3_EL2
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mrs_s x7, ICH_LR2_EL2
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mrs_s x6, ICH_LR1_EL2
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mrs_s x5, ICH_LR0_EL2
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adr x24, 1f
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add x24, x24, x23
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br x24
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1:
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str x20, [x3, #LR_OFFSET(15)]
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str x19, [x3, #LR_OFFSET(14)]
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str x18, [x3, #LR_OFFSET(13)]
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str x17, [x3, #LR_OFFSET(12)]
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str x16, [x3, #LR_OFFSET(11)]
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str x15, [x3, #LR_OFFSET(10)]
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str x14, [x3, #LR_OFFSET(9)]
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str x13, [x3, #LR_OFFSET(8)]
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str x12, [x3, #LR_OFFSET(7)]
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str x11, [x3, #LR_OFFSET(6)]
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str x10, [x3, #LR_OFFSET(5)]
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str x9, [x3, #LR_OFFSET(4)]
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str x8, [x3, #LR_OFFSET(3)]
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str x7, [x3, #LR_OFFSET(2)]
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str x6, [x3, #LR_OFFSET(1)]
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str x5, [x3, #LR_OFFSET(0)]
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tbnz w21, #29, 6f // 6 bits
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tbz w21, #30, 5f // 5 bits
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// 7 bits
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mrs_s x20, ICH_AP0R3_EL2
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str w20, [x3, #(VGIC_V3_CPU_AP0R + 3*4)]
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mrs_s x19, ICH_AP0R2_EL2
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str w19, [x3, #(VGIC_V3_CPU_AP0R + 2*4)]
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6: mrs_s x18, ICH_AP0R1_EL2
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str w18, [x3, #(VGIC_V3_CPU_AP0R + 1*4)]
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5: mrs_s x17, ICH_AP0R0_EL2
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str w17, [x3, #VGIC_V3_CPU_AP0R]
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tbnz w21, #29, 6f // 6 bits
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tbz w21, #30, 5f // 5 bits
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// 7 bits
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mrs_s x20, ICH_AP1R3_EL2
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str w20, [x3, #(VGIC_V3_CPU_AP1R + 3*4)]
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mrs_s x19, ICH_AP1R2_EL2
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str w19, [x3, #(VGIC_V3_CPU_AP1R + 2*4)]
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6: mrs_s x18, ICH_AP1R1_EL2
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str w18, [x3, #(VGIC_V3_CPU_AP1R + 1*4)]
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5: mrs_s x17, ICH_AP1R0_EL2
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str w17, [x3, #VGIC_V3_CPU_AP1R]
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// Restore SRE_EL1 access and re-enable SRE at EL1.
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mrs_s x5, ICC_SRE_EL2
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orr x5, x5, #ICC_SRE_EL2_ENABLE
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msr_s ICC_SRE_EL2, x5
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isb
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mov x5, #1
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msr_s ICC_SRE_EL1, x5
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.endm
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/*
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* Restore the VGIC CPU state from memory
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* x0: Register pointing to VCPU struct
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*/
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.macro restore_vgic_v3_state
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// Compute the address of struct vgic_cpu
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add x3, x0, #VCPU_VGIC_CPU
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// Restore all interesting registers
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ldr w4, [x3, #VGIC_V3_CPU_HCR]
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ldr w5, [x3, #VGIC_V3_CPU_VMCR]
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ldr w25, [x3, #VGIC_V3_CPU_SRE]
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msr_s ICC_SRE_EL1, x25
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// make sure SRE is valid before writing the other registers
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isb
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msr_s ICH_HCR_EL2, x4
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msr_s ICH_VMCR_EL2, x5
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mrs_s x21, ICH_VTR_EL2
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tbnz w21, #29, 6f // 6 bits
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tbz w21, #30, 5f // 5 bits
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// 7 bits
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ldr w20, [x3, #(VGIC_V3_CPU_AP1R + 3*4)]
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msr_s ICH_AP1R3_EL2, x20
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ldr w19, [x3, #(VGIC_V3_CPU_AP1R + 2*4)]
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msr_s ICH_AP1R2_EL2, x19
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6: ldr w18, [x3, #(VGIC_V3_CPU_AP1R + 1*4)]
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msr_s ICH_AP1R1_EL2, x18
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5: ldr w17, [x3, #VGIC_V3_CPU_AP1R]
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msr_s ICH_AP1R0_EL2, x17
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tbnz w21, #29, 6f // 6 bits
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tbz w21, #30, 5f // 5 bits
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// 7 bits
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ldr w20, [x3, #(VGIC_V3_CPU_AP0R + 3*4)]
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msr_s ICH_AP0R3_EL2, x20
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ldr w19, [x3, #(VGIC_V3_CPU_AP0R + 2*4)]
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msr_s ICH_AP0R2_EL2, x19
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6: ldr w18, [x3, #(VGIC_V3_CPU_AP0R + 1*4)]
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msr_s ICH_AP0R1_EL2, x18
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5: ldr w17, [x3, #VGIC_V3_CPU_AP0R]
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msr_s ICH_AP0R0_EL2, x17
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and w22, w21, #0xf
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mvn w22, w21
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ubfiz w23, w22, 2, 4 // w23 = (15 - ListRegs) * 4
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adr x24, 1f
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add x24, x24, x23
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br x24
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1:
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ldr x20, [x3, #LR_OFFSET(15)]
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ldr x19, [x3, #LR_OFFSET(14)]
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ldr x18, [x3, #LR_OFFSET(13)]
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ldr x17, [x3, #LR_OFFSET(12)]
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ldr x16, [x3, #LR_OFFSET(11)]
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ldr x15, [x3, #LR_OFFSET(10)]
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ldr x14, [x3, #LR_OFFSET(9)]
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ldr x13, [x3, #LR_OFFSET(8)]
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ldr x12, [x3, #LR_OFFSET(7)]
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ldr x11, [x3, #LR_OFFSET(6)]
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ldr x10, [x3, #LR_OFFSET(5)]
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ldr x9, [x3, #LR_OFFSET(4)]
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ldr x8, [x3, #LR_OFFSET(3)]
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ldr x7, [x3, #LR_OFFSET(2)]
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ldr x6, [x3, #LR_OFFSET(1)]
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ldr x5, [x3, #LR_OFFSET(0)]
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adr x24, 1f
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add x24, x24, x23
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br x24
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1:
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msr_s ICH_LR15_EL2, x20
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msr_s ICH_LR14_EL2, x19
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msr_s ICH_LR13_EL2, x18
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msr_s ICH_LR12_EL2, x17
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msr_s ICH_LR11_EL2, x16
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msr_s ICH_LR10_EL2, x15
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msr_s ICH_LR9_EL2, x14
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msr_s ICH_LR8_EL2, x13
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msr_s ICH_LR7_EL2, x12
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msr_s ICH_LR6_EL2, x11
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msr_s ICH_LR5_EL2, x10
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msr_s ICH_LR4_EL2, x9
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msr_s ICH_LR3_EL2, x8
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msr_s ICH_LR2_EL2, x7
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msr_s ICH_LR1_EL2, x6
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msr_s ICH_LR0_EL2, x5
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|
||||
// Ensure that the above will have reached the
|
||||
// (re)distributors. This ensure the guest will read
|
||||
// the correct values from the memory-mapped interface.
|
||||
isb
|
||||
dsb sy
|
||||
|
||||
// Prevent the guest from touching the GIC system registers
|
||||
// if SRE isn't enabled for GICv3 emulation
|
||||
cbnz x25, 1f
|
||||
mrs_s x5, ICC_SRE_EL2
|
||||
and x5, x5, #~ICC_SRE_EL2_ENABLE
|
||||
msr_s ICC_SRE_EL2, x5
|
||||
1:
|
||||
.endm
|
||||
|
||||
ENTRY(__save_vgic_v3_state)
|
||||
save_vgic_v3_state
|
||||
ret
|
||||
ENDPROC(__save_vgic_v3_state)
|
||||
|
||||
ENTRY(__restore_vgic_v3_state)
|
||||
restore_vgic_v3_state
|
||||
ret
|
||||
ENDPROC(__restore_vgic_v3_state)
|
||||
|
||||
ENTRY(__vgic_v3_get_ich_vtr_el2)
|
||||
mrs_s x0, ICH_VTR_EL2
|
||||
ret
|
||||
ENDPROC(__vgic_v3_get_ich_vtr_el2)
|
||||
|
||||
.popsection
|
||||
Loading…
Reference in a new issue