forked from mirrors/linux
pwm: Add support for Meson PWM Controller
Add support for the PWM controller found in the Amlogic SoCs. This driver supports the Meson8b and GXBB SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
This commit is contained in:
Neil Armstrong
Thierry Reding
parent
89394cc7c2
commit
211ed63075
3 changed files with 530 additions and 0 deletions
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@ -262,6 +262,15 @@ config PWM_LPSS_PLATFORM
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To compile this driver as a module, choose M here: the module
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To compile this driver as a module, choose M here: the module
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will be called pwm-lpss-platform.
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will be called pwm-lpss-platform.
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config PWM_MESON
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tristate "Amlogic Meson PWM driver"
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depends on ARCH_MESON
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help
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The platform driver for Amlogic Meson PWM controller.
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To compile this driver as a module, choose M here: the module
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will be called pwm-meson.
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config PWM_MTK_DISP
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config PWM_MTK_DISP
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tristate "MediaTek display PWM driver"
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tristate "MediaTek display PWM driver"
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depends on ARCH_MEDIATEK || COMPILE_TEST
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depends on ARCH_MEDIATEK || COMPILE_TEST
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@ -24,6 +24,7 @@ obj-$(CONFIG_PWM_LPC32XX) += pwm-lpc32xx.o
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obj-$(CONFIG_PWM_LPSS) += pwm-lpss.o
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obj-$(CONFIG_PWM_LPSS) += pwm-lpss.o
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obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-pci.o
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obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-pci.o
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obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o
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obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o
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obj-$(CONFIG_PWM_MESON) += pwm-meson.o
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obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o
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obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o
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obj-$(CONFIG_PWM_MXS) += pwm-mxs.o
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obj-$(CONFIG_PWM_MXS) += pwm-mxs.o
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obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o
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obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o
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520
drivers/pwm/pwm-meson.c
Normal file
520
drivers/pwm/pwm-meson.c
Normal file
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@ -0,0 +1,520 @@
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (C) 2014 Amlogic, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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* The full GNU General Public License is included in this distribution
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* in the file called COPYING.
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*
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* BSD LICENSE
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*
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (C) 2014 Amlogic, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#define REG_PWM_A 0x0
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#define REG_PWM_B 0x4
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#define PWM_HIGH_SHIFT 16
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#define REG_MISC_AB 0x8
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#define MISC_B_CLK_EN BIT(23)
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#define MISC_A_CLK_EN BIT(15)
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#define MISC_CLK_DIV_MASK 0x7f
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#define MISC_B_CLK_DIV_SHIFT 16
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#define MISC_A_CLK_DIV_SHIFT 8
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#define MISC_B_CLK_SEL_SHIFT 6
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#define MISC_A_CLK_SEL_SHIFT 4
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#define MISC_CLK_SEL_WIDTH 2
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#define MISC_B_EN BIT(1)
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#define MISC_A_EN BIT(0)
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static const unsigned int mux_reg_shifts[] = {
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MISC_A_CLK_SEL_SHIFT,
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MISC_B_CLK_SEL_SHIFT
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};
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struct meson_pwm_channel {
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unsigned int hi;
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unsigned int lo;
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u8 pre_div;
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struct pwm_state state;
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struct clk *clk_parent;
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struct clk_mux mux;
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struct clk *clk;
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};
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struct meson_pwm_data {
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const char * const *parent_names;
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};
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struct meson_pwm {
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struct pwm_chip chip;
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const struct meson_pwm_data *data;
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void __iomem *base;
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u8 inverter_mask;
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spinlock_t lock;
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};
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static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip)
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{
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return container_of(chip, struct meson_pwm, chip);
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}
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static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
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struct device *dev = chip->dev;
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int err;
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if (!channel)
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return -ENODEV;
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if (channel->clk_parent) {
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err = clk_set_parent(channel->clk, channel->clk_parent);
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if (err < 0) {
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dev_err(dev, "failed to set parent %s for %s: %d\n",
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__clk_get_name(channel->clk_parent),
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__clk_get_name(channel->clk), err);
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return err;
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}
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}
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err = clk_prepare_enable(channel->clk);
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if (err < 0) {
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dev_err(dev, "failed to enable clock %s: %d\n",
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__clk_get_name(channel->clk), err);
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return err;
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}
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chip->ops->get_state(chip, pwm, &channel->state);
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return 0;
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}
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static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
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if (channel)
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clk_disable_unprepare(channel->clk);
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}
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static int meson_pwm_calc(struct meson_pwm *meson,
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struct meson_pwm_channel *channel, unsigned int id,
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unsigned int duty, unsigned int period)
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{
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unsigned int pre_div, cnt, duty_cnt;
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unsigned long fin_freq = -1, fin_ns;
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if (~(meson->inverter_mask >> id) & 0x1)
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duty = period - duty;
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if (period == channel->state.period &&
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duty == channel->state.duty_cycle)
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return 0;
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fin_freq = clk_get_rate(channel->clk);
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if (fin_freq == 0) {
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dev_err(meson->chip.dev, "invalid source clock frequency\n");
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return -EINVAL;
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}
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dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq);
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fin_ns = NSEC_PER_SEC / fin_freq;
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/* Calc pre_div with the period */
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for (pre_div = 0; pre_div < MISC_CLK_DIV_MASK; pre_div++) {
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cnt = DIV_ROUND_CLOSEST(period, fin_ns * (pre_div + 1));
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dev_dbg(meson->chip.dev, "fin_ns=%lu pre_div=%u cnt=%u\n",
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fin_ns, pre_div, cnt);
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if (cnt <= 0xffff)
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break;
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}
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if (pre_div == MISC_CLK_DIV_MASK) {
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dev_err(meson->chip.dev, "unable to get period pre_div\n");
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return -EINVAL;
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}
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dev_dbg(meson->chip.dev, "period=%u pre_div=%u cnt=%u\n", period,
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pre_div, cnt);
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if (duty == period) {
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channel->pre_div = pre_div;
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channel->hi = cnt;
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channel->lo = 0;
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} else if (duty == 0) {
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channel->pre_div = pre_div;
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channel->hi = 0;
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channel->lo = cnt;
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} else {
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/* Then check is we can have the duty with the same pre_div */
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duty_cnt = DIV_ROUND_CLOSEST(duty, fin_ns * (pre_div + 1));
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if (duty_cnt > 0xffff) {
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dev_err(meson->chip.dev, "unable to get duty cycle\n");
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return -EINVAL;
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}
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dev_dbg(meson->chip.dev, "duty=%u pre_div=%u duty_cnt=%u\n",
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duty, pre_div, duty_cnt);
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channel->pre_div = pre_div;
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channel->hi = duty_cnt;
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channel->lo = cnt - duty_cnt;
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}
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return 0;
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}
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static void meson_pwm_enable(struct meson_pwm *meson,
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struct meson_pwm_channel *channel,
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unsigned int id)
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{
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u32 value, clk_shift, clk_enable, enable;
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unsigned int offset;
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switch (id) {
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case 0:
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clk_shift = MISC_A_CLK_DIV_SHIFT;
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clk_enable = MISC_A_CLK_EN;
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enable = MISC_A_EN;
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offset = REG_PWM_A;
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break;
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case 1:
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clk_shift = MISC_B_CLK_DIV_SHIFT;
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clk_enable = MISC_B_CLK_EN;
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enable = MISC_B_EN;
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offset = REG_PWM_B;
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break;
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}
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value = readl(meson->base + REG_MISC_AB);
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value &= ~(MISC_CLK_DIV_MASK << clk_shift);
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value |= channel->pre_div << clk_shift;
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value |= clk_enable;
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writel(value, meson->base + REG_MISC_AB);
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value = (channel->hi << PWM_HIGH_SHIFT) | channel->lo;
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writel(value, meson->base + offset);
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value = readl(meson->base + REG_MISC_AB);
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value |= enable;
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writel(value, meson->base + REG_MISC_AB);
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}
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static void meson_pwm_disable(struct meson_pwm *meson, unsigned int id)
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{
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u32 value, enable;
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switch (id) {
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case 0:
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enable = MISC_A_EN;
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break;
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case 1:
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enable = MISC_B_EN;
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break;
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}
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value = readl(meson->base + REG_MISC_AB);
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value &= ~enable;
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writel(value, meson->base + REG_MISC_AB);
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}
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static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
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struct meson_pwm *meson = to_meson_pwm(chip);
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unsigned long flags;
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int err = 0;
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if (!state)
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return -EINVAL;
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|
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spin_lock_irqsave(&meson->lock, flags);
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|
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if (!state->enabled) {
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meson_pwm_disable(meson, pwm->hwpwm);
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channel->state.enabled = false;
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|
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goto unlock;
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}
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|
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if (state->period != channel->state.period ||
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state->duty_cycle != channel->state.duty_cycle ||
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state->polarity != channel->state.polarity) {
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if (channel->state.enabled) {
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meson_pwm_disable(meson, pwm->hwpwm);
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channel->state.enabled = false;
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}
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if (state->polarity != channel->state.polarity) {
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if (state->polarity == PWM_POLARITY_NORMAL)
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meson->inverter_mask |= BIT(pwm->hwpwm);
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else
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meson->inverter_mask &= ~BIT(pwm->hwpwm);
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}
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err = meson_pwm_calc(meson, channel, pwm->hwpwm,
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state->duty_cycle, state->period);
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if (err < 0)
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goto unlock;
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channel->state.polarity = state->polarity;
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channel->state.period = state->period;
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channel->state.duty_cycle = state->duty_cycle;
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}
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if (state->enabled && !channel->state.enabled) {
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meson_pwm_enable(meson, channel, pwm->hwpwm);
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channel->state.enabled = true;
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}
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unlock:
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spin_unlock_irqrestore(&meson->lock, flags);
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|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
|
||||||
|
struct pwm_state *state)
|
||||||
|
{
|
||||||
|
struct meson_pwm *meson = to_meson_pwm(chip);
|
||||||
|
u32 value, mask;
|
||||||
|
|
||||||
|
if (!state)
|
||||||
|
return;
|
||||||
|
|
||||||
|
switch (pwm->hwpwm) {
|
||||||
|
case 0:
|
||||||
|
mask = MISC_A_EN;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 1:
|
||||||
|
mask = MISC_B_EN;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
value = readl(meson->base + REG_MISC_AB);
|
||||||
|
state->enabled = (value & mask) != 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct pwm_ops meson_pwm_ops = {
|
||||||
|
.request = meson_pwm_request,
|
||||||
|
.free = meson_pwm_free,
|
||||||
|
.apply = meson_pwm_apply,
|
||||||
|
.get_state = meson_pwm_get_state,
|
||||||
|
.owner = THIS_MODULE,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const pwm_meson8b_parent_names[] = {
|
||||||
|
"xtal", "vid_pll", "fclk_div4", "fclk_div3"
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct meson_pwm_data pwm_meson8b_data = {
|
||||||
|
.parent_names = pwm_meson8b_parent_names,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const char * const pwm_gxbb_parent_names[] = {
|
||||||
|
"xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct meson_pwm_data pwm_gxbb_data = {
|
||||||
|
.parent_names = pwm_gxbb_parent_names,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct of_device_id meson_pwm_matches[] = {
|
||||||
|
{ .compatible = "amlogic,meson8b-pwm", .data = &pwm_meson8b_data },
|
||||||
|
{ .compatible = "amlogic,meson-gxbb-pwm", .data = &pwm_gxbb_data },
|
||||||
|
{},
|
||||||
|
};
|
||||||
|
MODULE_DEVICE_TABLE(of, meson_pwm_matches);
|
||||||
|
|
||||||
|
static int meson_pwm_init_channels(struct meson_pwm *meson,
|
||||||
|
struct meson_pwm_channel *channels)
|
||||||
|
{
|
||||||
|
struct device *dev = meson->chip.dev;
|
||||||
|
struct device_node *np = dev->of_node;
|
||||||
|
struct clk_init_data init;
|
||||||
|
unsigned int i;
|
||||||
|
char name[255];
|
||||||
|
int err;
|
||||||
|
|
||||||
|
for (i = 0; i < meson->chip.npwm; i++) {
|
||||||
|
struct meson_pwm_channel *channel = &channels[i];
|
||||||
|
|
||||||
|
snprintf(name, sizeof(name), "%s#mux%u", np->full_name, i);
|
||||||
|
|
||||||
|
init.name = name;
|
||||||
|
init.ops = &clk_mux_ops;
|
||||||
|
init.flags = CLK_IS_BASIC;
|
||||||
|
init.parent_names = meson->data->parent_names;
|
||||||
|
init.num_parents = 1 << MISC_CLK_SEL_WIDTH;
|
||||||
|
|
||||||
|
channel->mux.reg = meson->base + REG_MISC_AB;
|
||||||
|
channel->mux.shift = mux_reg_shifts[i];
|
||||||
|
channel->mux.mask = BIT(MISC_CLK_SEL_WIDTH) - 1;
|
||||||
|
channel->mux.flags = 0;
|
||||||
|
channel->mux.lock = &meson->lock;
|
||||||
|
channel->mux.table = NULL;
|
||||||
|
channel->mux.hw.init = &init;
|
||||||
|
|
||||||
|
channel->clk = devm_clk_register(dev, &channel->mux.hw);
|
||||||
|
if (IS_ERR(channel->clk)) {
|
||||||
|
err = PTR_ERR(channel->clk);
|
||||||
|
dev_err(dev, "failed to register %s: %d\n", name, err);
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
snprintf(name, sizeof(name), "clkin%u", i);
|
||||||
|
|
||||||
|
channel->clk_parent = devm_clk_get(dev, name);
|
||||||
|
if (IS_ERR(channel->clk_parent)) {
|
||||||
|
err = PTR_ERR(channel->clk_parent);
|
||||||
|
if (err == -EPROBE_DEFER)
|
||||||
|
return err;
|
||||||
|
|
||||||
|
channel->clk_parent = NULL;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void meson_pwm_add_channels(struct meson_pwm *meson,
|
||||||
|
struct meson_pwm_channel *channels)
|
||||||
|
{
|
||||||
|
unsigned int i;
|
||||||
|
|
||||||
|
for (i = 0; i < meson->chip.npwm; i++)
|
||||||
|
pwm_set_chip_data(&meson->chip.pwms[i], &channels[i]);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int meson_pwm_probe(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
struct meson_pwm_channel *channels;
|
||||||
|
struct meson_pwm *meson;
|
||||||
|
struct resource *regs;
|
||||||
|
int err;
|
||||||
|
|
||||||
|
meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL);
|
||||||
|
if (!meson)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||||
|
meson->base = devm_ioremap_resource(&pdev->dev, regs);
|
||||||
|
if (IS_ERR(meson->base))
|
||||||
|
return PTR_ERR(meson->base);
|
||||||
|
|
||||||
|
meson->chip.dev = &pdev->dev;
|
||||||
|
meson->chip.ops = &meson_pwm_ops;
|
||||||
|
meson->chip.base = -1;
|
||||||
|
meson->chip.npwm = 2;
|
||||||
|
meson->chip.of_xlate = of_pwm_xlate_with_flags;
|
||||||
|
meson->chip.of_pwm_n_cells = 3;
|
||||||
|
|
||||||
|
meson->data = of_device_get_match_data(&pdev->dev);
|
||||||
|
meson->inverter_mask = BIT(meson->chip.npwm) - 1;
|
||||||
|
|
||||||
|
channels = devm_kcalloc(&pdev->dev, meson->chip.npwm, sizeof(*meson),
|
||||||
|
GFP_KERNEL);
|
||||||
|
if (!channels)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
err = meson_pwm_init_channels(meson, channels);
|
||||||
|
if (err < 0)
|
||||||
|
return err;
|
||||||
|
|
||||||
|
err = pwmchip_add(&meson->chip);
|
||||||
|
if (err < 0) {
|
||||||
|
dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err);
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
meson_pwm_add_channels(meson, channels);
|
||||||
|
|
||||||
|
platform_set_drvdata(pdev, meson);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int meson_pwm_remove(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
struct meson_pwm *meson = platform_get_drvdata(pdev);
|
||||||
|
|
||||||
|
return pwmchip_remove(&meson->chip);
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct platform_driver meson_pwm_driver = {
|
||||||
|
.driver = {
|
||||||
|
.name = "meson-pwm",
|
||||||
|
.of_match_table = meson_pwm_matches,
|
||||||
|
},
|
||||||
|
.probe = meson_pwm_probe,
|
||||||
|
.remove = meson_pwm_remove,
|
||||||
|
};
|
||||||
|
module_platform_driver(meson_pwm_driver);
|
||||||
|
|
||||||
|
MODULE_ALIAS("platform:meson-pwm");
|
||||||
|
MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver");
|
||||||
|
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
|
||||||
|
MODULE_LICENSE("Dual BSD/GPL");
|
||||||
Loading…
Reference in a new issue