forked from mirrors/linux
mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC
Add a new variant of the SDHI driver to support R-Car Gen3 with DMA via on-chip bus mastering. Since the DMAC is in a part of the SDHI module it is not suitable to be used via DMA Engine. Clearing of DM_CM_INFO1 after DMA thanks to Dirk Behme Cc: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Simon Horman
Ulf Hansson
parent
92d0f925e6
commit
2a68ea7896
5 changed files with 299 additions and 2 deletions
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@ -575,10 +575,29 @@ config MMC_SDHI
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depends on SUPERH || ARM || ARM64
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depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
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select MMC_TMIO_CORE
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select MMC_SDHI_SYS_DMAC if (SUPERH || ARM)
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select MMC_SDHI_INTERNAL_DMAC if ARM64
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help
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This provides support for the SDHI SD/SDIO controller found in
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Renesas SuperH, ARM and ARM64 based SoCs
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config MMC_SDHI_SYS_DMAC
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tristate "DMA for SDHI SD/SDIO controllers using SYS-DMAC"
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depends on MMC_SDHI
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help
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This provides DMA support for SDHI SD/SDIO controllers
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using SYS-DMAC via DMA Engine. This supports the controllers
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found in SuperH and Renesas ARM based SoCs.
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config MMC_SDHI_INTERNAL_DMAC
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tristate "DMA for SDHI SD/SDIO controllers using on-chip bus mastering"
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depends on ARM64 || COMPILE_TEST
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depends on MMC_SDHI
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help
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This provides DMA support for SDHI SD/SDIO controllers
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using on-chip bus mastering. This supports the controllers
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found in arm64 based SoCs.
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config MMC_CB710
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tristate "ENE CB710 MMC/SD Interface support"
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depends on PCI
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@ -36,7 +36,13 @@ obj-$(CONFIG_MMC_S3C) += s3cmci.o
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obj-$(CONFIG_MMC_SDRICOH_CS) += sdricoh_cs.o
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obj-$(CONFIG_MMC_TMIO) += tmio_mmc.o
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obj-$(CONFIG_MMC_TMIO_CORE) += tmio_mmc_core.o
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obj-$(CONFIG_MMC_SDHI) += renesas_sdhi_core.o renesas_sdhi_sys_dmac.o
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obj-$(CONFIG_MMC_SDHI) += renesas_sdhi_core.o
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ifeq ($(subst m,y,$(CONFIG_MMC_SDHI_SYS_DMAC)),y)
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obj-$(CONFIG_MMC_SDHI) += renesas_sdhi_sys_dmac.o
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endif
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ifeq ($(subst m,y,$(CONFIG_MMC_SDHI_INTERNAL_DMAC)),y)
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obj-$(CONFIG_MMC_SDHI) += renesas_sdhi_internal_dmac.o
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endif
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obj-$(CONFIG_MMC_CB710) += cb710-mmc.o
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obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc.o
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obj-$(CONFIG_SDH_BFIN) += bfin_sdh.o
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271
drivers/mmc/host/renesas_sdhi_internal_dmac.c
Normal file
271
drivers/mmc/host/renesas_sdhi_internal_dmac.c
Normal file
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@ -0,0 +1,271 @@
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/*
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* DMA support for Internal DMAC with SDHI SD/SDIO controller
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*
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* Copyright (C) 2016-17 Renesas Electronics Corporation
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* Copyright (C) 2016-17 Horms Solutions, Simon Horman
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/io-64-nonatomic-hi-lo.h>
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#include <linux/mfd/tmio.h>
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#include <linux/mmc/host.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/pagemap.h>
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#include <linux/scatterlist.h>
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#include "renesas_sdhi.h"
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#include "tmio_mmc.h"
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#define DM_CM_DTRAN_MODE 0x820
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#define DM_CM_DTRAN_CTRL 0x828
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#define DM_CM_RST 0x830
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#define DM_CM_INFO1 0x840
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#define DM_CM_INFO1_MASK 0x848
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#define DM_CM_INFO2 0x850
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#define DM_CM_INFO2_MASK 0x858
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#define DM_DTRAN_ADDR 0x880
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/* DM_CM_DTRAN_MODE */
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#define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */
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#define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "uptream" = for read commands */
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#define DTRAN_MODE_BUS_WID_TH (BIT(5) | BIT(4))
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#define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address */
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/* DM_CM_DTRAN_CTRL */
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#define DTRAN_CTRL_DM_START BIT(0)
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/* DM_CM_RST */
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#define RST_DTRANRST1 BIT(9)
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#define RST_DTRANRST0 BIT(8)
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#define RST_RESERVED_BITS GENMASK_ULL(32, 0)
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/* DM_CM_INFO1 and DM_CM_INFO1_MASK */
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#define INFO1_CLEAR 0
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#define INFO1_DTRANEND1 BIT(17)
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#define INFO1_DTRANEND0 BIT(16)
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/* DM_CM_INFO2 and DM_CM_INFO2_MASK */
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#define INFO2_DTRANERR1 BIT(17)
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#define INFO2_DTRANERR0 BIT(16)
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/*
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* Specification of this driver:
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* - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma
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* - Since this SDHI DMAC register set has 16 but 32-bit width, we
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* need a custom accessor.
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*/
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/* Definitions for sampling clocks */
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static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
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{
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.clk_rate = 0,
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.tap = 0x00000300,
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},
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};
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static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
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.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
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TMIO_MMC_CLK_ACTUAL | TMIO_MMC_MIN_RCAR2,
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.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
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MMC_CAP_CMD23,
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.bus_shift = 2,
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.scc_offset = 0x1000,
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.taps = rcar_gen3_scc_taps,
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.taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
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/* Gen3 SDHI DMAC can handle 0xffffffff blk count, but seg = 1 */
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.max_blk_count = 0xffffffff,
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.max_segs = 1,
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};
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static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
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{ .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
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{ .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
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{},
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};
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MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match);
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static void
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renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host,
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int addr, u64 val)
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{
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writeq(val, host->ctl + addr);
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}
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static void
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renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable)
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{
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if (!host->chan_tx || !host->chan_rx)
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return;
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if (!enable)
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renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1,
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INFO1_CLEAR);
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if (host->dma->enable)
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host->dma->enable(host, enable);
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}
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static void
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renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) {
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u64 val = RST_DTRANRST1 | RST_DTRANRST0;
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renesas_sdhi_internal_dmac_enable_dma(host, false);
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renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
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RST_RESERVED_BITS & ~val);
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renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
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RST_RESERVED_BITS | val);
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renesas_sdhi_internal_dmac_enable_dma(host, true);
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}
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static void
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renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) {
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tasklet_schedule(&host->dma_complete);
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}
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static void
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renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
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struct mmc_data *data)
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{
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struct scatterlist *sg = host->sg_ptr;
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u32 dtran_mode = DTRAN_MODE_BUS_WID_TH | DTRAN_MODE_ADDR_MODE;
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enum dma_data_direction dir;
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int ret;
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u32 irq_mask;
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/* This DMAC cannot handle if sg_len is not 1 */
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WARN_ON(host->sg_len > 1);
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/* This DMAC cannot handle if buffer is not 8-bytes alignment */
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if (!IS_ALIGNED(sg->offset, 8)) {
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host->force_pio = true;
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renesas_sdhi_internal_dmac_enable_dma(host, false);
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return;
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}
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if (data->flags & MMC_DATA_READ) {
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dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
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dir = DMA_FROM_DEVICE;
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irq_mask = TMIO_STAT_RXRDY;
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} else {
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dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
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dir = DMA_TO_DEVICE;
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irq_mask = TMIO_STAT_TXRQ;
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}
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ret = dma_map_sg(&host->pdev->dev, sg, host->sg_len, dir);
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if (ret < 0)
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return;
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renesas_sdhi_internal_dmac_enable_dma(host, true);
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/* disable PIO irqs to avoid "PIO IRQ in DMA mode!" */
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tmio_mmc_disable_mmc_irqs(host, irq_mask);
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/* set dma parameters */
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renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE,
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dtran_mode);
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renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR,
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sg->dma_address);
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}
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static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg)
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{
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struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
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tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
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/* start the DMAC */
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renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL,
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DTRAN_CTRL_DM_START);
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}
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static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
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{
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struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
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enum dma_data_direction dir;
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spin_lock_irq(&host->lock);
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if (!host->data)
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goto out;
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if (host->data->flags & MMC_DATA_READ)
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dir = DMA_FROM_DEVICE;
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else
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dir = DMA_TO_DEVICE;
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renesas_sdhi_internal_dmac_enable_dma(host, false);
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dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir);
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tmio_mmc_do_data_irq(host);
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out:
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spin_unlock_irq(&host->lock);
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}
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static void
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renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host,
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struct tmio_mmc_data *pdata)
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{
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/* Each value is set to non-zero to assume "enabling" each DMA */
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host->chan_rx = host->chan_tx = (void *)0xdeadbeaf;
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tasklet_init(&host->dma_complete,
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renesas_sdhi_internal_dmac_complete_tasklet_fn,
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(unsigned long)host);
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tasklet_init(&host->dma_issue,
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renesas_sdhi_internal_dmac_issue_tasklet_fn,
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(unsigned long)host);
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}
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static void
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renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host)
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{
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/* Each value is set to zero to assume "disabling" each DMA */
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host->chan_rx = host->chan_tx = NULL;
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}
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static struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = {
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.start = renesas_sdhi_internal_dmac_start_dma,
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.enable = renesas_sdhi_internal_dmac_enable_dma,
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.request = renesas_sdhi_internal_dmac_request_dma,
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.release = renesas_sdhi_internal_dmac_release_dma,
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.abort = renesas_sdhi_internal_dmac_abort_dma,
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.dataend = renesas_sdhi_internal_dmac_dataend_dma,
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};
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static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)
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{
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return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops);
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}
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static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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pm_runtime_force_resume)
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SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
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tmio_mmc_host_runtime_resume,
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NULL)
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};
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static struct platform_driver renesas_internal_dmac_sdhi_driver = {
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.driver = {
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.name = "renesas_sdhi_internal_dmac",
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.pm = &renesas_sdhi_internal_dmac_dev_pm_ops,
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.of_match_table = renesas_sdhi_internal_dmac_of_match,
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},
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.probe = renesas_sdhi_internal_dmac_probe,
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.remove = renesas_sdhi_remove,
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};
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module_platform_driver(renesas_internal_dmac_sdhi_driver);
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MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC");
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MODULE_AUTHOR("Yoshihiro Shimoda");
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MODULE_LICENSE("GPL v2");
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@ -1,5 +1,5 @@
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/*
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* DMA function for TMIO MMC implementations
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* DMA support use of SYS DMAC with SDHI SD/SDIO controller
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*
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* Copyright (C) 2016-17 Renesas Electronics Corporation
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* Copyright (C) 2016-17 Sang Engineering, Wolfram Sang
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@ -152,6 +152,7 @@ struct tmio_mmc_host {
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struct dma_chan *chan_rx;
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struct dma_chan *chan_tx;
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struct completion dma_dataend;
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struct tasklet_struct dma_complete;
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struct tasklet_struct dma_issue;
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struct scatterlist bounce_sg;
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u8 *bounce_buf;
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