forked from mirrors/linux
[POWERPC] Add tsi108 pci and platform device data register function
Add Tundra Semiconductor tsi108 pci and platform device data register function support. Signed-off-by: Alexandre Bounine <alexandreb@tundra.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> --- Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Zang Roy-r61911
Paul Mackerras
parent
c5d56332fd
commit
2b9d7467a6
4 changed files with 667 additions and 0 deletions
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@ -12,3 +12,4 @@ obj-$(CONFIG_U3_DART) += dart_iommu.o
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obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
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obj-$(CONFIG_PPC_83xx) += ipic.o
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obj-$(CONFIG_FSL_SOC) += fsl_soc.o
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obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
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145
arch/powerpc/sysdev/tsi108_dev.c
Normal file
145
arch/powerpc/sysdev/tsi108_dev.c
Normal file
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@ -0,0 +1,145 @@
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/*
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* tsi108/109 device setup code
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*
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* Maintained by Roy Zang < tie-fei.zang@freescale.com >
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/major.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <asm/tsi108.h>
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#include <asm/system.h>
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#include <asm/atomic.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/prom.h>
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#include <mm/mmu_decl.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt...) do { printk(fmt); } while(0)
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#else
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#define DBG(fmt...) do { } while(0)
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#endif
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static phys_addr_t tsi108_csr_base = -1;
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phys_addr_t get_csrbase(void)
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{
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struct device_node *tsi;
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if (tsi108_csr_base != -1)
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return tsi108_csr_base;
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tsi = of_find_node_by_type(NULL, "tsi-bridge");
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if (tsi) {
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unsigned int size;
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void *prop = get_property(tsi, "reg", &size);
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tsi108_csr_base = of_translate_address(tsi, prop);
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of_node_put(tsi);
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};
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return tsi108_csr_base;
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}
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u32 get_vir_csrbase(void)
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{
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return (u32) (ioremap(get_csrbase(), 0x10000));
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}
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EXPORT_SYMBOL(get_csrbase);
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EXPORT_SYMBOL(get_vir_csrbase);
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static int __init tsi108_eth_of_init(void)
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{
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struct device_node *np;
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unsigned int i;
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struct platform_device *tsi_eth_dev;
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struct resource res;
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int ret;
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for (np = NULL, i = 0;
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(np = of_find_compatible_node(np, "network", "tsi-ethernet")) != NULL;
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i++) {
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struct resource r[2];
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struct device_node *phy;
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hw_info tsi_eth_data;
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unsigned int *id;
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unsigned int *phy_id;
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void *mac_addr;
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phandle *ph;
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memset(r, 0, sizeof(r));
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memset(&tsi_eth_data, 0, sizeof(tsi_eth_data));
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ret = of_address_to_resource(np, 0, &r[0]);
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DBG("%s: name:start->end = %s:0x%lx-> 0x%lx\n",
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__FUNCTION__,r[0].name, r[0].start, r[0].end);
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if (ret)
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goto err;
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r[1].name = "tx";
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r[1].start = np->intrs[0].line;
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r[1].end = np->intrs[0].line;
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r[1].flags = IORESOURCE_IRQ;
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tsi_eth_dev =
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platform_device_register_simple("tsi-ethernet", i, &r[0],
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np->n_intrs + 1);
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if (IS_ERR(tsi_eth_dev)) {
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ret = PTR_ERR(tsi_eth_dev);
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goto err;
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}
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mac_addr = get_property(np, "address", NULL);
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memcpy(tsi_eth_data.mac_addr, mac_addr, 6);
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ph = (phandle *) get_property(np, "phy-handle", NULL);
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phy = of_find_node_by_phandle(*ph);
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if (phy == NULL) {
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ret = -ENODEV;
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goto unreg;
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}
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id = (u32 *) get_property(phy, "reg", NULL);
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phy_id = (u32 *) get_property(phy, "phy-id", NULL);
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ret = of_address_to_resource(phy, 0, &res);
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if (ret) {
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of_node_put(phy);
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goto unreg;
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}
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tsi_eth_data.regs = r[0].start;
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tsi_eth_data.phyregs = res.start;
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tsi_eth_data.phy = *phy_id;
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tsi_eth_data.irq_num = np->intrs[0].line;
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of_node_put(phy);
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ret =
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platform_device_add_data(tsi_eth_dev, &tsi_eth_data,
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sizeof(hw_info));
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if (ret)
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goto unreg;
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}
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return 0;
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unreg:
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platform_device_unregister(tsi_eth_dev);
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err:
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return ret;
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}
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arch_initcall(tsi108_eth_of_init);
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412
arch/powerpc/sysdev/tsi108_pci.c
Normal file
412
arch/powerpc/sysdev/tsi108_pci.c
Normal file
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@ -0,0 +1,412 @@
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/*
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* Common routines for Tundra Semiconductor TSI108 host bridge.
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*
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* 2004-2005 (c) Tundra Semiconductor Corp.
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* Author: Alex Bounine (alexandreb@tundra.com)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <asm/byteorder.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/uaccess.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/tsi108.h>
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#include <asm/tsi108_irq.h>
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#include <asm/prom.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(x...) printk(x)
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#else
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#define DBG(x...)
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#endif
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#define tsi_mk_config_addr(bus, devfunc, offset) \
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((((bus)<<16) | ((devfunc)<<8) | (offset & 0xfc)) + tsi108_pci_cfg_base)
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u32 tsi108_pci_cfg_base;
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u32 tsi108_csr_vir_base;
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extern u32 get_vir_csrbase(void);
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extern u32 tsi108_read_reg(u32 reg_offset);
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extern void tsi108_write_reg(u32 reg_offset, u32 val);
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int
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tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfunc,
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int offset, int len, u32 val)
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{
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volatile unsigned char *cfg_addr;
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if (ppc_md.pci_exclude_device)
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if (ppc_md.pci_exclude_device(bus->number, devfunc))
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return PCIBIOS_DEVICE_NOT_FOUND;
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cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
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devfunc, offset) |
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(offset & 0x03));
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#ifdef DEBUG
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printk("PCI CFG write : ");
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printk("%d:0x%x:0x%x ", bus->number, devfunc, offset);
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printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
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printk("data = 0x%08x\n", val);
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#endif
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switch (len) {
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case 1:
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out_8((u8 *) cfg_addr, val);
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break;
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case 2:
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out_le16((u16 *) cfg_addr, val);
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break;
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default:
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out_le32((u32 *) cfg_addr, val);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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void tsi108_clear_pci_error(u32 pci_cfg_base)
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{
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u32 err_stat, err_addr, pci_stat;
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/*
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* Quietly clear PB and PCI error flags set as result
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* of PCI/X configuration read requests.
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*/
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/* Read PB Error Log Registers */
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err_stat = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS);
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err_addr = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_AERR);
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if (err_stat & TSI108_PB_ERRCS_ES) {
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/* Clear error flag */
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tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS,
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TSI108_PB_ERRCS_ES);
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/* Clear read error reported in PB_ISR */
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tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ISR,
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TSI108_PB_ISR_PBS_RD_ERR);
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/* Clear PCI/X bus cfg errors if applicable */
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if ((err_addr & 0xFF000000) == pci_cfg_base) {
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pci_stat =
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tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR);
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tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR,
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pci_stat);
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}
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}
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return;
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}
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#define __tsi108_read_pci_config(x, addr, op) \
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__asm__ __volatile__( \
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" "op" %0,0,%1\n" \
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"1: eieio\n" \
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"2:\n" \
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".section .fixup,\"ax\"\n" \
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"3: li %0,-1\n" \
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" b 2b\n" \
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".section __ex_table,\"a\"\n" \
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" .align 2\n" \
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" .long 1b,3b\n" \
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".text" \
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: "=r"(x) : "r"(addr))
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int
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tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 * val)
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{
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volatile unsigned char *cfg_addr;
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u32 temp;
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if (ppc_md.pci_exclude_device)
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if (ppc_md.pci_exclude_device(bus->number, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
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devfn,
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offset) | (offset &
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0x03));
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switch (len) {
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case 1:
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__tsi108_read_pci_config(temp, cfg_addr, "lbzx");
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break;
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case 2:
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__tsi108_read_pci_config(temp, cfg_addr, "lhbrx");
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break;
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default:
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__tsi108_read_pci_config(temp, cfg_addr, "lwbrx");
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break;
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}
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*val = temp;
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#ifdef DEBUG
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if ((0xFFFFFFFF != temp) && (0xFFFF != temp) && (0xFF != temp)) {
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printk("PCI CFG read : ");
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printk("%d:0x%x:0x%x ", bus->number, devfn, offset);
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printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
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printk("data = 0x%x\n", *val);
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}
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#endif
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return PCIBIOS_SUCCESSFUL;
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}
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void tsi108_clear_pci_cfg_error(void)
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{
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tsi108_clear_pci_error(TSI108_PCI_CFG_BASE_PHYS);
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}
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static struct pci_ops tsi108_direct_pci_ops = {
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tsi108_direct_read_config,
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tsi108_direct_write_config
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};
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int __init tsi108_setup_pci(struct device_node *dev)
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{
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int len;
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struct pci_controller *hose;
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struct resource rsrc;
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int *bus_range;
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int primary = 0, has_address = 0;
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/* PCI Config mapping */
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tsi108_pci_cfg_base = (u32)ioremap(TSI108_PCI_CFG_BASE_PHYS,
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TSI108_PCI_CFG_SIZE);
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DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __FUNCTION__,
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tsi108_pci_cfg_base);
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/* Fetch host bridge registers address */
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has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
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/* Get bus range if any */
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bus_range = (int *)get_property(dev, "bus-range", &len);
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if (bus_range == NULL || len < 2 * sizeof(int)) {
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printk(KERN_WARNING "Can't get bus-range for %s, assume"
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" bus 0\n", dev->full_name);
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}
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hose = pcibios_alloc_controller();
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if (!hose) {
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printk("PCI Host bridge init failed\n");
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return -ENOMEM;
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}
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hose->arch_data = dev;
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hose->set_cfg_type = 1;
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hose->first_busno = bus_range ? bus_range[0] : 0;
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hose->last_busno = bus_range ? bus_range[1] : 0xff;
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(hose)->ops = &tsi108_direct_pci_ops;
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printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08lx. "
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"Firmware bus number: %d->%d\n",
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rsrc.start, hose->first_busno, hose->last_busno);
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/* Interpret the "ranges" property */
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/* This also maps the I/O region and sets isa_io/mem_base */
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pci_process_bridge_OF_ranges(hose, dev, primary);
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return 0;
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}
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/*
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* Low level utility functions
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*/
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static void tsi108_pci_int_mask(u_int irq)
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{
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u_int irp_cfg;
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int int_line = (irq - IRQ_PCI_INTAD_BASE);
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irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
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mb();
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irp_cfg |= (1 << int_line); /* INTx_DIR = output */
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irp_cfg &= ~(3 << (8 + (int_line * 2))); /* INTx_TYPE = unused */
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tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
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mb();
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irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
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}
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static void tsi108_pci_int_unmask(u_int irq)
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{
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u_int irp_cfg;
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int int_line = (irq - IRQ_PCI_INTAD_BASE);
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irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
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mb();
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irp_cfg &= ~(1 << int_line);
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irp_cfg |= (3 << (8 + (int_line * 2)));
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tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
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mb();
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}
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static void init_pci_source(void)
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{
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tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL,
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0x0000ff00);
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tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
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TSI108_PCI_IRP_ENABLE_P_INT);
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mb();
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}
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static inline int get_pci_source(void)
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{
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u_int temp = 0;
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int irq = -1;
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int i;
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u_int pci_irp_stat;
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static int mask = 0;
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/* Read PCI/X block interrupt status register */
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pci_irp_stat = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
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mb();
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if (pci_irp_stat & TSI108_PCI_IRP_STAT_P_INT) {
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/* Process Interrupt from PCI bus INTA# - INTD# lines */
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temp =
|
||||
tsi108_read_reg(TSI108_PCI_OFFSET +
|
||||
TSI108_PCI_IRP_INTAD) & 0xf;
|
||||
mb();
|
||||
for (i = 0; i < 4; i++, mask++) {
|
||||
if (temp & (1 << mask % 4)) {
|
||||
irq = IRQ_PCI_INTA + mask % 4;
|
||||
mask++;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable interrupts from PCI block */
|
||||
temp = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
|
||||
tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
|
||||
temp & ~TSI108_PCI_IRP_ENABLE_P_INT);
|
||||
mb();
|
||||
(void)tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
|
||||
mb();
|
||||
}
|
||||
#ifdef DEBUG
|
||||
else {
|
||||
printk("TSI108_PIC: error in TSI108_PCI_IRP_STAT\n");
|
||||
pci_irp_stat =
|
||||
tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
|
||||
temp =
|
||||
tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_INTAD);
|
||||
mb();
|
||||
printk(">> stat=0x%08x intad=0x%08x ", pci_irp_stat, temp);
|
||||
temp =
|
||||
tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
|
||||
mb();
|
||||
printk("cfg_ctl=0x%08x ", temp);
|
||||
temp =
|
||||
tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
|
||||
mb();
|
||||
printk("irp_enable=0x%08x\n", temp);
|
||||
}
|
||||
#endif /* end of DEBUG */
|
||||
|
||||
return irq;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Linux descriptor level callbacks
|
||||
*/
|
||||
|
||||
static void tsi108_pci_irq_enable(u_int irq)
|
||||
{
|
||||
tsi108_pci_int_unmask(irq);
|
||||
}
|
||||
|
||||
static void tsi108_pci_irq_disable(u_int irq)
|
||||
{
|
||||
tsi108_pci_int_mask(irq);
|
||||
}
|
||||
|
||||
static void tsi108_pci_irq_ack(u_int irq)
|
||||
{
|
||||
tsi108_pci_int_mask(irq);
|
||||
}
|
||||
|
||||
static void tsi108_pci_irq_end(u_int irq)
|
||||
{
|
||||
tsi108_pci_int_unmask(irq);
|
||||
|
||||
/* Enable interrupts from PCI block */
|
||||
tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
|
||||
tsi108_read_reg(TSI108_PCI_OFFSET +
|
||||
TSI108_PCI_IRP_ENABLE) |
|
||||
TSI108_PCI_IRP_ENABLE_P_INT);
|
||||
mb();
|
||||
}
|
||||
|
||||
/*
|
||||
* Interrupt controller descriptor for cascaded PCI interrupt controller.
|
||||
*/
|
||||
|
||||
struct hw_interrupt_type tsi108_pci_irq = {
|
||||
.typename = "tsi108_PCI_int",
|
||||
.enable = tsi108_pci_irq_enable,
|
||||
.disable = tsi108_pci_irq_disable,
|
||||
.ack = tsi108_pci_irq_ack,
|
||||
.end = tsi108_pci_irq_end,
|
||||
};
|
||||
|
||||
/*
|
||||
* Exported functions
|
||||
*/
|
||||
|
||||
/*
|
||||
* The Tsi108 PCI interrupts initialization routine.
|
||||
*
|
||||
* The INTA# - INTD# interrupts on the PCI bus are reported by the PCI block
|
||||
* to the MPIC using single interrupt source (IRQ_TSI108_PCI). Therefore the
|
||||
* PCI block has to be treated as a cascaded interrupt controller connected
|
||||
* to the MPIC.
|
||||
*/
|
||||
|
||||
void __init tsi108_pci_int_init(void)
|
||||
{
|
||||
u_int i;
|
||||
|
||||
DBG("Tsi108_pci_int_init: initializing PCI interrupts\n");
|
||||
|
||||
for (i = 0; i < NUM_PCI_IRQS; i++) {
|
||||
irq_desc[i + IRQ_PCI_INTAD_BASE].handler = &tsi108_pci_irq;
|
||||
irq_desc[i + IRQ_PCI_INTAD_BASE].status |= IRQ_LEVEL;
|
||||
}
|
||||
|
||||
init_pci_source();
|
||||
}
|
||||
|
||||
int tsi108_irq_cascade(struct pt_regs *regs, void *unused)
|
||||
{
|
||||
return get_pci_source();
|
||||
}
|
||||
109
include/asm-powerpc/tsi108.h
Normal file
109
include/asm-powerpc/tsi108.h
Normal file
|
|
@ -0,0 +1,109 @@
|
|||
/*
|
||||
* include/asm-ppc/tsi108.h
|
||||
*
|
||||
* common routine and memory layout for Tundra TSI108(Grendel) host bridge
|
||||
* memory controller.
|
||||
*
|
||||
* Author: Jacob Pan (jacob.pan@freescale.com)
|
||||
* Alex Bounine (alexandreb@tundra.com)
|
||||
* 2004 (c) Freescale Semiconductor Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
#ifndef __PPC_KERNEL_TSI108_H
|
||||
#define __PPC_KERNEL_TSI108_H
|
||||
|
||||
#include <asm/pci-bridge.h>
|
||||
|
||||
/* Size of entire register space */
|
||||
#define TSI108_REG_SIZE (0x10000)
|
||||
|
||||
/* Sizes of register spaces for individual blocks */
|
||||
#define TSI108_HLP_SIZE 0x1000
|
||||
#define TSI108_PCI_SIZE 0x1000
|
||||
#define TSI108_CLK_SIZE 0x1000
|
||||
#define TSI108_PB_SIZE 0x1000
|
||||
#define TSI108_SD_SIZE 0x1000
|
||||
#define TSI108_DMA_SIZE 0x1000
|
||||
#define TSI108_ETH_SIZE 0x1000
|
||||
#define TSI108_I2C_SIZE 0x400
|
||||
#define TSI108_MPIC_SIZE 0x400
|
||||
#define TSI108_UART0_SIZE 0x200
|
||||
#define TSI108_GPIO_SIZE 0x200
|
||||
#define TSI108_UART1_SIZE 0x200
|
||||
|
||||
/* Offsets within Tsi108(A) CSR space for individual blocks */
|
||||
#define TSI108_HLP_OFFSET 0x0000
|
||||
#define TSI108_PCI_OFFSET 0x1000
|
||||
#define TSI108_CLK_OFFSET 0x2000
|
||||
#define TSI108_PB_OFFSET 0x3000
|
||||
#define TSI108_SD_OFFSET 0x4000
|
||||
#define TSI108_DMA_OFFSET 0x5000
|
||||
#define TSI108_ETH_OFFSET 0x6000
|
||||
#define TSI108_I2C_OFFSET 0x7000
|
||||
#define TSI108_MPIC_OFFSET 0x7400
|
||||
#define TSI108_UART0_OFFSET 0x7800
|
||||
#define TSI108_GPIO_OFFSET 0x7A00
|
||||
#define TSI108_UART1_OFFSET 0x7C00
|
||||
|
||||
/* Tsi108 registers used by common code components */
|
||||
#define TSI108_PCI_CSR (0x004)
|
||||
#define TSI108_PCI_IRP_CFG_CTL (0x180)
|
||||
#define TSI108_PCI_IRP_STAT (0x184)
|
||||
#define TSI108_PCI_IRP_ENABLE (0x188)
|
||||
#define TSI108_PCI_IRP_INTAD (0x18C)
|
||||
|
||||
#define TSI108_PCI_IRP_STAT_P_INT (0x00400000)
|
||||
#define TSI108_PCI_IRP_ENABLE_P_INT (0x00400000)
|
||||
|
||||
#define TSI108_CG_PWRUP_STATUS (0x234)
|
||||
|
||||
#define TSI108_PB_ISR (0x00C)
|
||||
#define TSI108_PB_ERRCS (0x404)
|
||||
#define TSI108_PB_AERR (0x408)
|
||||
|
||||
#define TSI108_PB_ERRCS_ES (1 << 1)
|
||||
#define TSI108_PB_ISR_PBS_RD_ERR (1 << 8)
|
||||
|
||||
#define TSI108_PCI_CFG_BASE_PHYS (0xfb000000)
|
||||
#define TSI108_PCI_CFG_SIZE (0x01000000)
|
||||
/* Global variables */
|
||||
|
||||
extern u32 tsi108_pci_cfg_base;
|
||||
/* Exported functions */
|
||||
|
||||
extern int tsi108_bridge_init(struct pci_controller *hose, uint phys_csr_base);
|
||||
extern unsigned long tsi108_get_mem_size(void);
|
||||
extern unsigned long tsi108_get_cpu_clk(void);
|
||||
extern unsigned long tsi108_get_sdc_clk(void);
|
||||
extern int tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfn,
|
||||
int offset, int len, u32 val);
|
||||
extern int tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn,
|
||||
int offset, int len, u32 * val);
|
||||
extern void tsi108_clear_pci_error(u32 pci_cfg_base);
|
||||
|
||||
extern phys_addr_t get_csrbase(void);
|
||||
|
||||
typedef struct {
|
||||
u32 regs; /* hw registers base address */
|
||||
u32 phyregs; /* phy registers base address */
|
||||
u16 phy; /* phy address */
|
||||
u16 irq_num; /* irq number */
|
||||
u8 mac_addr[6]; /* phy mac address */
|
||||
} hw_info;
|
||||
|
||||
extern u32 get_vir_csrbase(void);
|
||||
extern u32 tsi108_csr_vir_base;
|
||||
|
||||
extern inline u32 tsi108_read_reg(u32 reg_offset)
|
||||
{
|
||||
return in_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset));
|
||||
}
|
||||
|
||||
extern inline void tsi108_write_reg(u32 reg_offset, u32 val)
|
||||
{
|
||||
out_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset), val);
|
||||
}
|
||||
|
||||
#endif /* __PPC_KERNEL_TSI108_H */
|
||||
Loading…
Reference in a new issue