forked from mirrors/linux
PCI: imx6: Add support for i.MX8MQ
Add code needed to support i.MX8MQ variant. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com>
This commit is contained in:
Andrey Smirnov
Lorenzo Pieralisi
parent
4c458bb347
commit
2d8ed461db
3 changed files with 79 additions and 5 deletions
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@ -9,6 +9,7 @@ Required properties:
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- "fsl,imx6sx-pcie",
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- "fsl,imx6qp-pcie"
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- "fsl,imx7d-pcie"
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- "fsl,imx8mq-pcie"
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- reg: base address and length of the PCIe controller
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- interrupts: A list of interrupt outputs of the controller. Must contain an
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entry for each entry in the interrupt-names property.
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@ -45,7 +46,7 @@ Additional required properties for imx6sx-pcie:
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PCIE_PHY power domains
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- power-domain-names: Must be "pcie", "pcie_phy"
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Additional required properties for imx7d-pcie:
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Additional required properties for imx7d-pcie and imx8mq-pcie:
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- power-domains: Must be set to a phandle pointing to PCIE_PHY power domain
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- resets: Must contain phandles to PCIe-related reset lines exposed by SRC
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IP block
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@ -89,8 +89,8 @@ config PCI_EXYNOS
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select PCIE_DW_HOST
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config PCI_IMX6
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bool "Freescale i.MX6/7 PCIe controller"
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depends on SOC_IMX6Q || SOC_IMX7D || (ARM && COMPILE_TEST)
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bool "Freescale i.MX6/7/8 PCIe controller"
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depends on SOC_IMX6Q || SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIE_DW_HOST
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@ -8,6 +8,7 @@
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* Author: Sean Cross <xobs@kosagi.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/gpio.h>
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@ -32,6 +33,12 @@
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#include "pcie-designware.h"
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#define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9)
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#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
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#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
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#define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8)
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#define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000
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#define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
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enum imx6_pcie_variants {
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@ -39,6 +46,7 @@ enum imx6_pcie_variants {
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IMX6SX,
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IMX6QP,
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IMX7D,
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IMX8MQ,
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};
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#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
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@ -58,6 +66,7 @@ struct imx6_pcie {
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struct clk *pcie_inbound_axi;
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struct clk *pcie;
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struct regmap *iomuxc_gpr;
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u32 controller_id;
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struct reset_control *pciephy_reset;
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struct reset_control *apps_reset;
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struct reset_control *turnoff_reset;
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@ -275,6 +284,7 @@ static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
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pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
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}
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#ifdef CONFIG_ARM
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/* Added for PCI abort handling */
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static int imx6q_pcie_abort_handler(unsigned long addr,
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unsigned int fsr, struct pt_regs *regs)
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@ -308,6 +318,7 @@ static int imx6q_pcie_abort_handler(unsigned long addr,
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return 1;
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}
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#endif
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static int imx6_pcie_attach_pd(struct device *dev)
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{
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@ -352,6 +363,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
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switch (imx6_pcie->drvdata->variant) {
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case IMX7D:
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case IMX8MQ:
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reset_control_assert(imx6_pcie->pciephy_reset);
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reset_control_assert(imx6_pcie->apps_reset);
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break;
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@ -386,10 +398,17 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
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}
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}
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static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
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{
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WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ);
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return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
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}
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static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
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{
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struct dw_pcie *pci = imx6_pcie->pci;
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struct device *dev = pci->dev;
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unsigned int offset;
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int ret = 0;
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switch (imx6_pcie->drvdata->variant) {
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@ -420,6 +439,19 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
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break;
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case IMX7D:
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break;
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case IMX8MQ:
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offset = imx6_pcie_grp_offset(imx6_pcie);
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/*
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* Set the over ride low and enabled
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* make sure that REF_CLK is turned on.
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*/
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regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
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IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
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0);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
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IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
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IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
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break;
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}
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return ret;
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@ -496,6 +528,9 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
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}
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switch (imx6_pcie->drvdata->variant) {
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case IMX8MQ:
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reset_control_deassert(imx6_pcie->pciephy_reset);
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break;
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case IMX7D:
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reset_control_deassert(imx6_pcie->pciephy_reset);
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imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
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@ -531,9 +566,37 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
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}
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}
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static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
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{
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unsigned int mask, val;
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if (imx6_pcie->drvdata->variant == IMX8MQ &&
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imx6_pcie->controller_id == 1) {
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mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE;
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val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
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PCI_EXP_TYPE_ROOT_PORT);
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} else {
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mask = IMX6Q_GPR12_DEVICE_TYPE;
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val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE,
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PCI_EXP_TYPE_ROOT_PORT);
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}
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
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}
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static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
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{
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switch (imx6_pcie->drvdata->variant) {
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case IMX8MQ:
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/*
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* TODO: Currently this code assumes external
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* oscillator is being used
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*/
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regmap_update_bits(imx6_pcie->iomuxc_gpr,
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imx6_pcie_grp_offset(imx6_pcie),
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IMX8MQ_GPR_PCIE_REF_USE_PAD,
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IMX8MQ_GPR_PCIE_REF_USE_PAD);
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break;
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case IMX7D:
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
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@ -569,8 +632,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
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break;
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}
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
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imx6_pcie_configure_type(imx6_pcie);
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}
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static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
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@ -667,6 +729,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
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IMX6Q_GPR12_PCIE_CTL_2);
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break;
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case IMX7D:
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case IMX8MQ:
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reset_control_deassert(imx6_pcie->apps_reset);
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break;
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}
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@ -1002,6 +1065,10 @@ static int imx6_pcie_probe(struct platform_device *pdev)
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}
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break;
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case IMX7D:
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case IMX8MQ:
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if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
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imx6_pcie->controller_id = 1;
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imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev,
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"pciephy");
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if (IS_ERR(imx6_pcie->pciephy_reset)) {
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@ -1117,6 +1184,9 @@ static const struct imx6_pcie_drvdata drvdata[] = {
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[IMX7D] = {
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.variant = IMX7D,
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},
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[IMX8MQ] = {
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.variant = IMX8MQ,
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},
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};
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static const struct of_device_id imx6_pcie_of_match[] = {
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@ -1124,6 +1194,7 @@ static const struct of_device_id imx6_pcie_of_match[] = {
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{ .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
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{ .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
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{ .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
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{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], } ,
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{},
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};
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@ -1140,6 +1211,7 @@ static struct platform_driver imx6_pcie_driver = {
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static int __init imx6_pcie_init(void)
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{
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#ifdef CONFIG_ARM
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/*
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* Since probe() can be deferred we need to make sure that
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* hook_fault_code is not called after __init memory is freed
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@ -1149,6 +1221,7 @@ static int __init imx6_pcie_init(void)
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*/
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hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0,
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"external abort on non-linefetch");
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#endif
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return platform_driver_register(&imx6_pcie_driver);
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}
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