forked from mirrors/linux
powerpc/usb: fix bug of CPU hang when missing USB PHY clock
when missing USB PHY clock, kernel booting up will hang during USB initialization. We should check USBGP[PHY_CLK_VALID] bit to avoid CPU hanging in this case. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Shengzhou Liu
Greg Kroah-Hartman
parent
67990472c7
commit
3735ba8db8
3 changed files with 42 additions and 18 deletions
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@ -210,11 +210,11 @@ static void usb_hcd_fsl_remove(struct usb_hcd *hcd,
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usb_put_hcd(hcd);
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}
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static void ehci_fsl_setup_phy(struct usb_hcd *hcd,
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static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
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enum fsl_usb2_phy_modes phy_mode,
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unsigned int port_offset)
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{
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u32 portsc, temp;
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u32 portsc;
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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void __iomem *non_ehci = hcd->regs;
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struct device *dev = hcd->self.controller;
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@ -232,9 +232,15 @@ static void ehci_fsl_setup_phy(struct usb_hcd *hcd,
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case FSL_USB2_PHY_ULPI:
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if (pdata->controller_ver) {
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/* controller version 1.6 or above */
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temp = in_be32(non_ehci + FSL_SOC_USB_CTRL);
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out_be32(non_ehci + FSL_SOC_USB_CTRL, temp |
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USB_CTRL_USB_EN | ULPI_PHY_CLK_SEL);
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setbits32(non_ehci + FSL_SOC_USB_CTRL,
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ULPI_PHY_CLK_SEL);
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/*
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* Due to controller issue of PHY_CLK_VALID in ULPI
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* mode, we set USB_CTRL_USB_EN before checking
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* PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work.
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*/
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clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
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UTMI_PHY_EN, USB_CTRL_USB_EN);
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}
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portsc |= PORT_PTS_ULPI;
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break;
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@ -247,9 +253,7 @@ static void ehci_fsl_setup_phy(struct usb_hcd *hcd,
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case FSL_USB2_PHY_UTMI:
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if (pdata->controller_ver) {
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/* controller version 1.6 or above */
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temp = in_be32(non_ehci + FSL_SOC_USB_CTRL);
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out_be32(non_ehci + FSL_SOC_USB_CTRL, temp |
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UTMI_PHY_EN | USB_CTRL_USB_EN);
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setbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);
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mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to
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become stable - 10ms*/
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}
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@ -262,23 +266,34 @@ static void ehci_fsl_setup_phy(struct usb_hcd *hcd,
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case FSL_USB2_PHY_NONE:
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break;
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}
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if ((pdata->controller_ver) && ((phy_mode == FSL_USB2_PHY_ULPI) ||
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(phy_mode == FSL_USB2_PHY_UTMI))) {
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/* check PHY_CLK_VALID to get phy clk valid */
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if (!spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) &
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PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0)) {
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printk(KERN_WARNING "fsl-ehci: USB PHY clock invalid\n");
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return -EINVAL;
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}
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}
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ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
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if (phy_mode != FSL_USB2_PHY_ULPI)
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setbits32(non_ehci + FSL_SOC_USB_CTRL, USB_CTRL_USB_EN);
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return 0;
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}
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static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
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static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
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{
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struct usb_hcd *hcd = ehci_to_hcd(ehci);
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struct fsl_usb2_platform_data *pdata;
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void __iomem *non_ehci = hcd->regs;
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u32 temp;
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pdata = hcd->self.controller->platform_data;
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/* Enable PHY interface in the control reg. */
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if (pdata->have_sysif_regs) {
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temp = in_be32(non_ehci + FSL_SOC_USB_CTRL);
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out_be32(non_ehci + FSL_SOC_USB_CTRL, temp | 0x00000004);
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/*
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* Turn on cache snooping hardware, since some PowerPC platforms
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* wholly rely on hardware to deal with cache coherent
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@ -293,7 +308,8 @@ static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
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if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
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(pdata->operating_mode == FSL_USB2_DR_OTG))
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ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0);
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if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
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return -EINVAL;
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if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
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unsigned int chip, rev, svr;
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@ -307,9 +323,12 @@ static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
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ehci->has_fsl_port_bug = 1;
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if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
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ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0);
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if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
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return -EINVAL;
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if (pdata->port_enables & FSL_USB2_PORT1_ENABLED)
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ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1);
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if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1))
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return -EINVAL;
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}
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if (pdata->have_sysif_regs) {
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@ -322,12 +341,15 @@ static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
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#endif
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out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001);
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}
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return 0;
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}
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/* called after powerup, by probe or system-pm "wakeup" */
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static int ehci_fsl_reinit(struct ehci_hcd *ehci)
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{
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ehci_fsl_usb_setup(ehci);
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if (ehci_fsl_usb_setup(ehci))
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return -EINVAL;
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ehci_port_power(ehci, 0);
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return 0;
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@ -61,4 +61,5 @@
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#define PLL_RESET (1<<8)
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#define UTMI_PHY_EN (1<<9)
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#define ULPI_PHY_CLK_SEL (1<<10)
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#define PHY_CLK_VALID (1<<17)
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#endif /* _EHCI_FSL_H */
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@ -19,6 +19,7 @@
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#define FSL_UTMI_PHY_DLY 10 /*As per P1010RM, delay for UTMI
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PHY CLK to become stable - 10ms*/
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#define FSL_USB_PHY_CLK_TIMEOUT 1000 /* uSec */
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#define FSL_USB_VER_OLD 0
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#define FSL_USB_VER_1_6 1
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#define FSL_USB_VER_2_2 2
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