forked from mirrors/linux
		
	net: stmmac: fix FPE events losing
The status bits of register MAC_FPE_CTRL_STS are clear on read. Using
32-bit read for MAC_FPE_CTRL_STS in dwmac5_fpe_configure() and
dwmac5_fpe_send_mpacket() clear the status bits. Then the stmmac interrupt
handler missing FPE event status and leads to FPE handshaking failure and
retries.
To avoid clear status bits of MAC_FPE_CTRL_STS in dwmac5_fpe_configure()
and dwmac5_fpe_send_mpacket(), add fpe_csr to stmmac_fpe_cfg structure to
cache the control bits of MAC_FPE_CTRL_STS and to avoid reading
MAC_FPE_CTRL_STS in those methods.
Fixes: 5a5586112b ("net: stmmac: support FPE link partner hand-shaking procedure")
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Signed-off-by: Jianheng Zhang <Jianheng.Zhang@synopsys.com>
Link: https://lore.kernel.org/r/CY5PR12MB637225A7CF529D5BE0FBE59CBF81A@CY5PR12MB6372.namprd12.prod.outlook.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
			
			
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					 7 changed files with 36 additions and 30 deletions
				
			
		|  | @ -710,28 +710,22 @@ void dwmac5_est_irq_status(void __iomem *ioaddr, struct net_device *dev, | ||||||
| 	} | 	} | ||||||
| } | } | ||||||
| 
 | 
 | ||||||
| void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq, | void dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, | ||||||
|  | 			  u32 num_txq, u32 num_rxq, | ||||||
| 			  bool enable) | 			  bool enable) | ||||||
| { | { | ||||||
| 	u32 value; | 	u32 value; | ||||||
| 
 | 
 | ||||||
| 	if (!enable) { | 	if (enable) { | ||||||
| 		value = readl(ioaddr + MAC_FPE_CTRL_STS); | 		cfg->fpe_csr = EFPE; | ||||||
| 
 | 		value = readl(ioaddr + GMAC_RXQ_CTRL1); | ||||||
| 		value &= ~EFPE; | 		value &= ~GMAC_RXQCTRL_FPRQ; | ||||||
| 
 | 		value |= (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT; | ||||||
| 		writel(value, ioaddr + MAC_FPE_CTRL_STS); | 		writel(value, ioaddr + GMAC_RXQ_CTRL1); | ||||||
| 		return; | 	} else { | ||||||
|  | 		cfg->fpe_csr = 0; | ||||||
| 	} | 	} | ||||||
| 
 | 	writel(cfg->fpe_csr, ioaddr + MAC_FPE_CTRL_STS); | ||||||
| 	value = readl(ioaddr + GMAC_RXQ_CTRL1); |  | ||||||
| 	value &= ~GMAC_RXQCTRL_FPRQ; |  | ||||||
| 	value |= (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT; |  | ||||||
| 	writel(value, ioaddr + GMAC_RXQ_CTRL1); |  | ||||||
| 
 |  | ||||||
| 	value = readl(ioaddr + MAC_FPE_CTRL_STS); |  | ||||||
| 	value |= EFPE; |  | ||||||
| 	writel(value, ioaddr + MAC_FPE_CTRL_STS); |  | ||||||
| } | } | ||||||
| 
 | 
 | ||||||
| int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev) | int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev) | ||||||
|  | @ -741,6 +735,9 @@ int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev) | ||||||
| 
 | 
 | ||||||
| 	status = FPE_EVENT_UNKNOWN; | 	status = FPE_EVENT_UNKNOWN; | ||||||
| 
 | 
 | ||||||
|  | 	/* Reads from the MAC_FPE_CTRL_STS register should only be performed
 | ||||||
|  | 	 * here, since the status flags of MAC_FPE_CTRL_STS are "clear on read" | ||||||
|  | 	 */ | ||||||
| 	value = readl(ioaddr + MAC_FPE_CTRL_STS); | 	value = readl(ioaddr + MAC_FPE_CTRL_STS); | ||||||
| 
 | 
 | ||||||
| 	if (value & TRSP) { | 	if (value & TRSP) { | ||||||
|  | @ -766,19 +763,15 @@ int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev) | ||||||
| 	return status; | 	return status; | ||||||
| } | } | ||||||
| 
 | 
 | ||||||
| void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, enum stmmac_mpacket_type type) | void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, | ||||||
|  | 			     enum stmmac_mpacket_type type) | ||||||
| { | { | ||||||
| 	u32 value; | 	u32 value = cfg->fpe_csr; | ||||||
| 
 | 
 | ||||||
| 	value = readl(ioaddr + MAC_FPE_CTRL_STS); | 	if (type == MPACKET_VERIFY) | ||||||
| 
 |  | ||||||
| 	if (type == MPACKET_VERIFY) { |  | ||||||
| 		value &= ~SRSP; |  | ||||||
| 		value |= SVER; | 		value |= SVER; | ||||||
| 	} else { | 	else if (type == MPACKET_RESPONSE) | ||||||
| 		value &= ~SVER; |  | ||||||
| 		value |= SRSP; | 		value |= SRSP; | ||||||
| 	} |  | ||||||
| 
 | 
 | ||||||
| 	writel(value, ioaddr + MAC_FPE_CTRL_STS); | 	writel(value, ioaddr + MAC_FPE_CTRL_STS); | ||||||
| } | } | ||||||
|  |  | ||||||
|  | @ -153,9 +153,11 @@ int dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg, | ||||||
| 			 unsigned int ptp_rate); | 			 unsigned int ptp_rate); | ||||||
| void dwmac5_est_irq_status(void __iomem *ioaddr, struct net_device *dev, | void dwmac5_est_irq_status(void __iomem *ioaddr, struct net_device *dev, | ||||||
| 			   struct stmmac_extra_stats *x, u32 txqcnt); | 			   struct stmmac_extra_stats *x, u32 txqcnt); | ||||||
| void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq, | void dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, | ||||||
|  | 			  u32 num_txq, u32 num_rxq, | ||||||
| 			  bool enable); | 			  bool enable); | ||||||
| void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, | void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, | ||||||
|  | 			     struct stmmac_fpe_cfg *cfg, | ||||||
| 			     enum stmmac_mpacket_type type); | 			     enum stmmac_mpacket_type type); | ||||||
| int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev); | int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev); | ||||||
| 
 | 
 | ||||||
|  |  | ||||||
|  | @ -1484,7 +1484,8 @@ static int dwxgmac3_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg, | ||||||
| 	return 0; | 	return 0; | ||||||
| } | } | ||||||
| 
 | 
 | ||||||
| static void dwxgmac3_fpe_configure(void __iomem *ioaddr, u32 num_txq, | static void dwxgmac3_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, | ||||||
|  | 				   u32 num_txq, | ||||||
| 				   u32 num_rxq, bool enable) | 				   u32 num_rxq, bool enable) | ||||||
| { | { | ||||||
| 	u32 value; | 	u32 value; | ||||||
|  |  | ||||||
|  | @ -412,9 +412,11 @@ struct stmmac_ops { | ||||||
| 			     unsigned int ptp_rate); | 			     unsigned int ptp_rate); | ||||||
| 	void (*est_irq_status)(void __iomem *ioaddr, struct net_device *dev, | 	void (*est_irq_status)(void __iomem *ioaddr, struct net_device *dev, | ||||||
| 			       struct stmmac_extra_stats *x, u32 txqcnt); | 			       struct stmmac_extra_stats *x, u32 txqcnt); | ||||||
| 	void (*fpe_configure)(void __iomem *ioaddr, u32 num_txq, u32 num_rxq, | 	void (*fpe_configure)(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, | ||||||
|  | 			      u32 num_txq, u32 num_rxq, | ||||||
| 			      bool enable); | 			      bool enable); | ||||||
| 	void (*fpe_send_mpacket)(void __iomem *ioaddr, | 	void (*fpe_send_mpacket)(void __iomem *ioaddr, | ||||||
|  | 				 struct stmmac_fpe_cfg *cfg, | ||||||
| 				 enum stmmac_mpacket_type type); | 				 enum stmmac_mpacket_type type); | ||||||
| 	int (*fpe_irq_status)(void __iomem *ioaddr, struct net_device *dev); | 	int (*fpe_irq_status)(void __iomem *ioaddr, struct net_device *dev); | ||||||
| }; | }; | ||||||
|  |  | ||||||
|  | @ -964,7 +964,8 @@ static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up) | ||||||
| 	bool *hs_enable = &fpe_cfg->hs_enable; | 	bool *hs_enable = &fpe_cfg->hs_enable; | ||||||
| 
 | 
 | ||||||
| 	if (is_up && *hs_enable) { | 	if (is_up && *hs_enable) { | ||||||
| 		stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY); | 		stmmac_fpe_send_mpacket(priv, priv->ioaddr, fpe_cfg, | ||||||
|  | 					MPACKET_VERIFY); | ||||||
| 	} else { | 	} else { | ||||||
| 		*lo_state = FPE_STATE_OFF; | 		*lo_state = FPE_STATE_OFF; | ||||||
| 		*lp_state = FPE_STATE_OFF; | 		*lp_state = FPE_STATE_OFF; | ||||||
|  | @ -5839,6 +5840,7 @@ static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) | ||||||
| 		/* If user has requested FPE enable, quickly response */ | 		/* If user has requested FPE enable, quickly response */ | ||||||
| 		if (*hs_enable) | 		if (*hs_enable) | ||||||
| 			stmmac_fpe_send_mpacket(priv, priv->ioaddr, | 			stmmac_fpe_send_mpacket(priv, priv->ioaddr, | ||||||
|  | 						fpe_cfg, | ||||||
| 						MPACKET_RESPONSE); | 						MPACKET_RESPONSE); | ||||||
| 	} | 	} | ||||||
| 
 | 
 | ||||||
|  | @ -7263,6 +7265,7 @@ static void stmmac_fpe_lp_task(struct work_struct *work) | ||||||
| 		if (*lo_state == FPE_STATE_ENTERING_ON && | 		if (*lo_state == FPE_STATE_ENTERING_ON && | ||||||
| 		    *lp_state == FPE_STATE_ENTERING_ON) { | 		    *lp_state == FPE_STATE_ENTERING_ON) { | ||||||
| 			stmmac_fpe_configure(priv, priv->ioaddr, | 			stmmac_fpe_configure(priv, priv->ioaddr, | ||||||
|  | 					     fpe_cfg, | ||||||
| 					     priv->plat->tx_queues_to_use, | 					     priv->plat->tx_queues_to_use, | ||||||
| 					     priv->plat->rx_queues_to_use, | 					     priv->plat->rx_queues_to_use, | ||||||
| 					     *enable); | 					     *enable); | ||||||
|  | @ -7281,6 +7284,7 @@ static void stmmac_fpe_lp_task(struct work_struct *work) | ||||||
| 			netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT, | 			netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT, | ||||||
| 				    *lo_state, *lp_state); | 				    *lo_state, *lp_state); | ||||||
| 			stmmac_fpe_send_mpacket(priv, priv->ioaddr, | 			stmmac_fpe_send_mpacket(priv, priv->ioaddr, | ||||||
|  | 						fpe_cfg, | ||||||
| 						MPACKET_VERIFY); | 						MPACKET_VERIFY); | ||||||
| 		} | 		} | ||||||
| 		/* Sleep then retry */ | 		/* Sleep then retry */ | ||||||
|  | @ -7295,6 +7299,7 @@ void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable) | ||||||
| 	if (priv->plat->fpe_cfg->hs_enable != enable) { | 	if (priv->plat->fpe_cfg->hs_enable != enable) { | ||||||
| 		if (enable) { | 		if (enable) { | ||||||
| 			stmmac_fpe_send_mpacket(priv, priv->ioaddr, | 			stmmac_fpe_send_mpacket(priv, priv->ioaddr, | ||||||
|  | 						priv->plat->fpe_cfg, | ||||||
| 						MPACKET_VERIFY); | 						MPACKET_VERIFY); | ||||||
| 		} else { | 		} else { | ||||||
| 			priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF; | 			priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF; | ||||||
|  | @ -7755,6 +7760,7 @@ int stmmac_suspend(struct device *dev) | ||||||
| 	if (priv->dma_cap.fpesel) { | 	if (priv->dma_cap.fpesel) { | ||||||
| 		/* Disable FPE */ | 		/* Disable FPE */ | ||||||
| 		stmmac_fpe_configure(priv, priv->ioaddr, | 		stmmac_fpe_configure(priv, priv->ioaddr, | ||||||
|  | 				     priv->plat->fpe_cfg, | ||||||
| 				     priv->plat->tx_queues_to_use, | 				     priv->plat->tx_queues_to_use, | ||||||
| 				     priv->plat->rx_queues_to_use, false); | 				     priv->plat->rx_queues_to_use, false); | ||||||
| 
 | 
 | ||||||
|  |  | ||||||
|  | @ -1079,6 +1079,7 @@ static int tc_setup_taprio(struct stmmac_priv *priv, | ||||||
| 
 | 
 | ||||||
| 	priv->plat->fpe_cfg->enable = false; | 	priv->plat->fpe_cfg->enable = false; | ||||||
| 	stmmac_fpe_configure(priv, priv->ioaddr, | 	stmmac_fpe_configure(priv, priv->ioaddr, | ||||||
|  | 			     priv->plat->fpe_cfg, | ||||||
| 			     priv->plat->tx_queues_to_use, | 			     priv->plat->tx_queues_to_use, | ||||||
| 			     priv->plat->rx_queues_to_use, | 			     priv->plat->rx_queues_to_use, | ||||||
| 			     false); | 			     false); | ||||||
|  |  | ||||||
|  | @ -175,6 +175,7 @@ struct stmmac_fpe_cfg { | ||||||
| 	bool hs_enable;				/* FPE handshake enable */ | 	bool hs_enable;				/* FPE handshake enable */ | ||||||
| 	enum stmmac_fpe_state lp_fpe_state;	/* Link Partner FPE state */ | 	enum stmmac_fpe_state lp_fpe_state;	/* Link Partner FPE state */ | ||||||
| 	enum stmmac_fpe_state lo_fpe_state;	/* Local station FPE state */ | 	enum stmmac_fpe_state lo_fpe_state;	/* Local station FPE state */ | ||||||
|  | 	u32 fpe_csr;				/* MAC_FPE_CTRL_STS reg cache */ | ||||||
| }; | }; | ||||||
| 
 | 
 | ||||||
| struct stmmac_safety_feature_cfg { | struct stmmac_safety_feature_cfg { | ||||||
|  |  | ||||||
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	 Jianheng Zhang
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