forked from mirrors/linux
PCI: Add pci_bus_addr_t
David Ahern reported thatd63e2e1f3d("sparc/PCI: Clip bridge windows to fit in upstream windows") fails to boot on sparc/T5-8: pci 0000:06:00.0: reg 0x184: can't handle BAR above 4GB (bus address 0x110204000) The problem is that sparc64 assumed that dma_addr_t only needed to hold DMA addresses, i.e., bus addresses returned via the DMA API (dma_map_single(), etc.), while the PCI core assumed dma_addr_t could hold *any* bus address, including raw BAR values. On sparc64, all DMA addresses fit in 32 bits, so dma_addr_t is a 32-bit type. However, BAR values can be 64 bits wide, so they don't fit in a dma_addr_t.d63e2e1f3dadded new checking that tripped over this mismatch. Add pci_bus_addr_t, which is wide enough to hold any PCI bus address, including both raw BAR values and DMA addresses. This will be 64 bits on 64-bit platforms and on platforms with a 64-bit dma_addr_t. Then dma_addr_t only needs to be wide enough to hold addresses from the DMA API. [bhelgaas: changelog, bugzilla, Kconfig to ensure pci_bus_addr_t is at least as wide as dma_addr_t, documentation] Fixes:d63e2e1f3d("sparc/PCI: Clip bridge windows to fit in upstream windows") Fixes:23b13bc76f("PCI: Fail safely if we can't handle BARs larger than 4GB") Link: http://lkml.kernel.org/r/CAE9FiQU1gJY1LYrxs+ma5LCTEEe4xmtjRG0aXJ9K_Tsu+m9Wuw@mail.gmail.com Link: http://lkml.kernel.org/r/1427857069-6789-1-git-send-email-yinghai@kernel.org Link: https://bugzilla.kernel.org/show_bug.cgi?id=96231 Reported-by: David Ahern <david.ahern@oracle.com> Tested-by: David Ahern <david.ahern@oracle.com> Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: David S. Miller <davem@davemloft.net> CC: stable@vger.kernel.org # v3.19+
This commit is contained in:
Yinghai Lu
Bjorn Helgaas
parent
5ebe6afaf0
commit
3a9ad0b4fd
7 changed files with 66 additions and 43 deletions
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@ -25,13 +25,18 @@ physical addresses. These are the addresses in /proc/iomem. The physical
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address is not directly useful to a driver; it must use ioremap() to map
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the space and produce a virtual address.
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I/O devices use a third kind of address: a "bus address" or "DMA address".
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If a device has registers at an MMIO address, or if it performs DMA to read
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or write system memory, the addresses used by the device are bus addresses.
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In some systems, bus addresses are identical to CPU physical addresses, but
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in general they are not. IOMMUs and host bridges can produce arbitrary
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I/O devices use a third kind of address: a "bus address". If a device has
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registers at an MMIO address, or if it performs DMA to read or write system
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memory, the addresses used by the device are bus addresses. In some
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systems, bus addresses are identical to CPU physical addresses, but in
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general they are not. IOMMUs and host bridges can produce arbitrary
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mappings between physical and bus addresses.
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From a device's point of view, DMA uses the bus address space, but it may
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be restricted to a subset of that space. For example, even if a system
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supports 64-bit addresses for main memory and PCI BARs, it may use an IOMMU
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so devices only need to use 32-bit DMA addresses.
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Here's a picture and some examples:
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CPU CPU Bus
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@ -72,11 +77,11 @@ can use virtual address X to access the buffer, but the device itself
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cannot because DMA doesn't go through the CPU virtual memory system.
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In some simple systems, the device can do DMA directly to physical address
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Y. But in many others, there is IOMMU hardware that translates bus
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Y. But in many others, there is IOMMU hardware that translates DMA
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addresses to physical addresses, e.g., it translates Z to Y. This is part
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of the reason for the DMA API: the driver can give a virtual address X to
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an interface like dma_map_single(), which sets up any required IOMMU
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mapping and returns the bus address Z. The driver then tells the device to
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mapping and returns the DMA address Z. The driver then tells the device to
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do DMA to Z, and the IOMMU maps it to the buffer at address Y in system
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RAM.
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@ -98,7 +103,7 @@ First of all, you should make sure
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#include <linux/dma-mapping.h>
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is in your driver, which provides the definition of dma_addr_t. This type
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can hold any valid DMA or bus address for the platform and should be used
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can hold any valid DMA address for the platform and should be used
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everywhere you hold a DMA address returned from the DMA mapping functions.
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What memory is DMA'able?
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@ -316,7 +321,7 @@ There are two types of DMA mappings:
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Think of "consistent" as "synchronous" or "coherent".
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The current default is to return consistent memory in the low 32
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bits of the bus space. However, for future compatibility you should
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bits of the DMA space. However, for future compatibility you should
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set the consistent mask even if this default is fine for your
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driver.
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@ -403,7 +408,7 @@ dma_alloc_coherent() returns two values: the virtual address which you
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can use to access it from the CPU and dma_handle which you pass to the
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card.
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The CPU virtual address and the DMA bus address are both
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The CPU virtual address and the DMA address are both
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guaranteed to be aligned to the smallest PAGE_SIZE order which
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is greater than or equal to the requested size. This invariant
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exists (for example) to guarantee that if you allocate a chunk
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@ -645,8 +650,8 @@ PLEASE NOTE: The 'nents' argument to the dma_unmap_sg call must be
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dma_map_sg call.
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Every dma_map_{single,sg}() call should have its dma_unmap_{single,sg}()
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counterpart, because the bus address space is a shared resource and
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you could render the machine unusable by consuming all bus addresses.
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counterpart, because the DMA address space is a shared resource and
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you could render the machine unusable by consuming all DMA addresses.
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If you need to use the same streaming DMA region multiple times and touch
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the data in between the DMA transfers, the buffer needs to be synced
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@ -18,10 +18,10 @@ Part I - dma_ API
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To get the dma_ API, you must #include <linux/dma-mapping.h>. This
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provides dma_addr_t and the interfaces described below.
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A dma_addr_t can hold any valid DMA or bus address for the platform. It
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can be given to a device to use as a DMA source or target. A CPU cannot
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reference a dma_addr_t directly because there may be translation between
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its physical address space and the bus address space.
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A dma_addr_t can hold any valid DMA address for the platform. It can be
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given to a device to use as a DMA source or target. A CPU cannot reference
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a dma_addr_t directly because there may be translation between its physical
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address space and the DMA address space.
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Part Ia - Using large DMA-coherent buffers
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------------------------------------------
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@ -42,7 +42,7 @@ It returns a pointer to the allocated region (in the processor's virtual
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address space) or NULL if the allocation failed.
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It also returns a <dma_handle> which may be cast to an unsigned integer the
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same width as the bus and given to the device as the bus address base of
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same width as the bus and given to the device as the DMA address base of
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the region.
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Note: consistent memory can be expensive on some platforms, and the
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@ -193,7 +193,7 @@ dma_map_single(struct device *dev, void *cpu_addr, size_t size,
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enum dma_data_direction direction)
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Maps a piece of processor virtual memory so it can be accessed by the
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device and returns the bus address of the memory.
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device and returns the DMA address of the memory.
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The direction for both APIs may be converted freely by casting.
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However the dma_ API uses a strongly typed enumerator for its
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@ -212,20 +212,20 @@ contiguous piece of memory. For this reason, memory to be mapped by
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this API should be obtained from sources which guarantee it to be
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physically contiguous (like kmalloc).
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Further, the bus address of the memory must be within the
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Further, the DMA address of the memory must be within the
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dma_mask of the device (the dma_mask is a bit mask of the
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addressable region for the device, i.e., if the bus address of
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the memory ANDed with the dma_mask is still equal to the bus
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addressable region for the device, i.e., if the DMA address of
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the memory ANDed with the dma_mask is still equal to the DMA
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address, then the device can perform DMA to the memory). To
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ensure that the memory allocated by kmalloc is within the dma_mask,
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the driver may specify various platform-dependent flags to restrict
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the bus address range of the allocation (e.g., on x86, GFP_DMA
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guarantees to be within the first 16MB of available bus addresses,
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the DMA address range of the allocation (e.g., on x86, GFP_DMA
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guarantees to be within the first 16MB of available DMA addresses,
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as required by ISA devices).
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Note also that the above constraints on physical contiguity and
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dma_mask may not apply if the platform has an IOMMU (a device which
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maps an I/O bus address to a physical memory address). However, to be
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maps an I/O DMA address to a physical memory address). However, to be
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portable, device driver writers may *not* assume that such an IOMMU
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exists.
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@ -296,7 +296,7 @@ reduce current DMA mapping usage or delay and try again later).
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dma_map_sg(struct device *dev, struct scatterlist *sg,
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int nents, enum dma_data_direction direction)
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Returns: the number of bus address segments mapped (this may be shorter
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Returns: the number of DMA address segments mapped (this may be shorter
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than <nents> passed in if some elements of the scatter/gather list are
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physically or virtually adjacent and an IOMMU maps them with a single
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entry).
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@ -340,7 +340,7 @@ must be the same as those and passed in to the scatter/gather mapping
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API.
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Note: <nents> must be the number you passed in, *not* the number of
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bus address entries returned.
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DMA address entries returned.
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void
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dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size,
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@ -507,7 +507,7 @@ it's asked for coherent memory for this device.
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phys_addr is the CPU physical address to which the memory is currently
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assigned (this will be ioremapped so the CPU can access the region).
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device_addr is the bus address the device needs to be programmed
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device_addr is the DMA address the device needs to be programmed
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with to actually address this memory (this will be handed out as the
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dma_addr_t in dma_alloc_coherent()).
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@ -1,6 +1,10 @@
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#
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# PCI configuration
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#
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config PCI_BUS_ADDR_T_64BIT
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def_bool y if (ARCH_DMA_ADDR_T_64BIT || 64BIT)
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depends on PCI
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config PCI_MSI
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bool "Message Signaled Interrupts (MSI and MSI-X)"
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depends on PCI
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@ -92,11 +92,11 @@ void pci_bus_remove_resources(struct pci_bus *bus)
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}
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static struct pci_bus_region pci_32_bit = {0, 0xffffffffULL};
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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#ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
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static struct pci_bus_region pci_64_bit = {0,
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(dma_addr_t) 0xffffffffffffffffULL};
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static struct pci_bus_region pci_high = {(dma_addr_t) 0x100000000ULL,
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(dma_addr_t) 0xffffffffffffffffULL};
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(pci_bus_addr_t) 0xffffffffffffffffULL};
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static struct pci_bus_region pci_high = {(pci_bus_addr_t) 0x100000000ULL,
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(pci_bus_addr_t) 0xffffffffffffffffULL};
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#endif
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/*
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@ -200,7 +200,7 @@ int pci_bus_alloc_resource(struct pci_bus *bus, struct resource *res,
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resource_size_t),
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void *alignf_data)
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{
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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#ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
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int rc;
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if (res->flags & IORESOURCE_MEM_64) {
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@ -254,8 +254,8 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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}
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if (res->flags & IORESOURCE_MEM_64) {
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if ((sizeof(dma_addr_t) < 8 || sizeof(resource_size_t) < 8) &&
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sz64 > 0x100000000ULL) {
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if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
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&& sz64 > 0x100000000ULL) {
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res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
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res->start = 0;
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res->end = 0;
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@ -264,7 +264,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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goto out;
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}
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if ((sizeof(dma_addr_t) < 8) && l) {
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if ((sizeof(pci_bus_addr_t) < 8) && l) {
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/* Above 32-bit boundary; try to reallocate */
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res->flags |= IORESOURCE_UNSET;
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res->start = 0;
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@ -399,7 +399,7 @@ static void pci_read_bridge_mmio_pref(struct pci_bus *child)
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struct pci_dev *dev = child->self;
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u16 mem_base_lo, mem_limit_lo;
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u64 base64, limit64;
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dma_addr_t base, limit;
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pci_bus_addr_t base, limit;
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struct pci_bus_region region;
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struct resource *res;
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@ -426,8 +426,8 @@ static void pci_read_bridge_mmio_pref(struct pci_bus *child)
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}
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}
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base = (dma_addr_t) base64;
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limit = (dma_addr_t) limit64;
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base = (pci_bus_addr_t) base64;
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limit = (pci_bus_addr_t) limit64;
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if (base != base64) {
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dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
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@ -577,9 +577,15 @@ int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
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int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
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int reg, int len, u32 val);
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#ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
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typedef u64 pci_bus_addr_t;
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#else
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typedef u32 pci_bus_addr_t;
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#endif
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struct pci_bus_region {
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dma_addr_t start;
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dma_addr_t end;
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pci_bus_addr_t start;
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pci_bus_addr_t end;
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};
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struct pci_dynids {
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@ -1128,7 +1134,7 @@ int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
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int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
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static inline dma_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
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static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
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{
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struct pci_bus_region region;
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@ -139,12 +139,20 @@ typedef unsigned long blkcnt_t;
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*/
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#define pgoff_t unsigned long
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/* A dma_addr_t can hold any valid DMA or bus address for the platform */
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/*
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* A dma_addr_t can hold any valid DMA address, i.e., any address returned
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* by the DMA API.
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*
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* If the DMA API only uses 32-bit addresses, dma_addr_t need only be 32
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* bits wide. Bus addresses, e.g., PCI BARs, may be wider than 32 bits,
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* but drivers do memory-mapped I/O to ioremapped kernel virtual addresses,
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* so they don't care about the size of the actual bus addresses.
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*/
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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typedef u64 dma_addr_t;
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#else
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typedef u32 dma_addr_t;
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#endif /* dma_addr_t */
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#endif
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typedef unsigned __bitwise__ gfp_t;
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typedef unsigned __bitwise__ fmode_t;
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