forked from mirrors/linux
		
	clk: socfpga: update clk.h so for Arria10 platform to use
There are 5 possible parent clocks for the SoCFPGA Arria10. Move the define SYSMGR_SDMMC_CTRL_SET and streq() to clk.h so that the Arria clock driver can use. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
		
							parent
							
								
									004cbb475f
								
							
						
					
					
						commit
						5611a5ba8e
					
				
					 2 changed files with 5 additions and 5 deletions
				
			
		| 
						 | 
					@ -32,14 +32,10 @@
 | 
				
			||||||
#define SOCFPGA_MMC_CLK			"sdmmc_clk"
 | 
					#define SOCFPGA_MMC_CLK			"sdmmc_clk"
 | 
				
			||||||
#define SOCFPGA_GPIO_DB_CLK_OFFSET	0xA8
 | 
					#define SOCFPGA_GPIO_DB_CLK_OFFSET	0xA8
 | 
				
			||||||
 | 
					
 | 
				
			||||||
#define streq(a, b) (strcmp((a), (b)) == 0)
 | 
					 | 
				
			||||||
 | 
					 | 
				
			||||||
#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
 | 
					#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
 | 
				
			||||||
 | 
					
 | 
				
			||||||
/* SDMMC Group for System Manager defines */
 | 
					/* SDMMC Group for System Manager defines */
 | 
				
			||||||
#define SYSMGR_SDMMCGRP_CTRL_OFFSET    0x108
 | 
					#define SYSMGR_SDMMCGRP_CTRL_OFFSET    0x108
 | 
				
			||||||
#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
 | 
					 | 
				
			||||||
	((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
 | 
					 | 
				
			||||||
 | 
					
 | 
				
			||||||
static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
 | 
					static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
 | 
				
			||||||
{
 | 
					{
 | 
				
			||||||
| 
						 | 
					
 | 
				
			||||||
| 
						 | 
					@ -26,9 +26,13 @@
 | 
				
			||||||
#define CLKMGR_L4SRC		0x70
 | 
					#define CLKMGR_L4SRC		0x70
 | 
				
			||||||
#define CLKMGR_PERPLL_SRC	0xAC
 | 
					#define CLKMGR_PERPLL_SRC	0xAC
 | 
				
			||||||
 | 
					
 | 
				
			||||||
#define SOCFPGA_MAX_PARENTS		3
 | 
					#define SOCFPGA_MAX_PARENTS		5
 | 
				
			||||||
#define div_mask(width) ((1 << (width)) - 1)
 | 
					#define div_mask(width) ((1 << (width)) - 1)
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					#define streq(a, b) (strcmp((a), (b)) == 0)
 | 
				
			||||||
 | 
					#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
 | 
				
			||||||
 | 
						((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
 | 
				
			||||||
 | 
					
 | 
				
			||||||
extern void __iomem *clk_mgr_base_addr;
 | 
					extern void __iomem *clk_mgr_base_addr;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
void __init socfpga_pll_init(struct device_node *node);
 | 
					void __init socfpga_pll_init(struct device_node *node);
 | 
				
			||||||
| 
						 | 
					
 | 
				
			||||||
		Loading…
	
		Reference in a new issue