forked from mirrors/linux
		
	spi: stm32: Add 'SPI_SIMPLEX_RX', 'SPI_3WIRE_RX' support for stm32f4
in l3gd20 driver startup, there is a setup failed error return from
stm32 spi driver
     "
     [    2.687630] st-gyro-spi spi0.0: supply vdd not found, using dummy
     regulator
     [    2.696869] st-gyro-spi spi0.0: supply vddio not found, using dummy
     regulator
     [    2.706707] spi_stm32 40015000.spi: SPI transfer setup failed
     [    2.713741] st-gyro-spi spi0.0: SPI transfer failed: -22
     [    2.721096] spi_master spi0: failed to transfer one message from queue
     [    2.729268] iio iio:device0: failed to read Who-Am-I register.
     [    2.737504] st-gyro-spi: probe of spi0.0 failed with error -22
     "
after debug into spi-stm32 driver, st-gyro-spi split two steps to read
l3gd20 id
first: send command to l3gd20 with read id command in tx_buf, rx_buf
is null.
second: read id with tx_buf is null, rx_buf not null.
so, for second step, stm32 driver recongise this process as 'SPI_SIMPLE_RX'
from stm32_spi_communication_type(), but there is no related process for this
type in stm32f4_spi_set_mode(), then we get error from
stm32_spi_transfer_one_setup().
we can use two method to fix this bug.
1, use stm32 spi's "In unidirectional receive-only mode (BIDIMODE=0 and
RXONLY=1)". but as our code running in sdram, the read latency is too large
to get so many receive overrun error in interrupts handler.
2, use stm32 spi's "In full-duplex (BIDIMODE=0 and RXONLY=0)", as tx_buf is
null, so add flag 'SPI_MASTER_MUST_TX' to spi master.
Change since V4:
1 remove dummy data sent out by stm32 spi driver
2 add flag 'SPI_MASTER_MUST_TX' to spi master
Signed-off-by: dillon min <dillon.minfei@gmail.com>
Link: https://lore.kernel.org/r/1590378348-8115-8-git-send-email-dillon.minfei@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
			
			
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					 1 changed files with 15 additions and 4 deletions
				
			
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					@ -811,7 +811,9 @@ static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id)
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		mask |= STM32F4_SPI_SR_TXE;
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							mask |= STM32F4_SPI_SR_TXE;
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	}
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						}
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	if (!spi->cur_usedma && spi->cur_comm == SPI_FULL_DUPLEX) {
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						if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX ||
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									spi->cur_comm == SPI_SIMPLEX_RX ||
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									spi->cur_comm == SPI_3WIRE_RX)) {
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		/* TXE flag is set and is handled when RXNE flag occurs */
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							/* TXE flag is set and is handled when RXNE flag occurs */
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		sr &= ~STM32F4_SPI_SR_TXE;
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							sr &= ~STM32F4_SPI_SR_TXE;
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		mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR;
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							mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR;
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					@ -850,7 +852,7 @@ static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id)
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		stm32f4_spi_read_rx(spi);
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							stm32f4_spi_read_rx(spi);
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		if (spi->rx_len == 0)
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							if (spi->rx_len == 0)
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			end = true;
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								end = true;
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		else /* Load data for discontinuous mode */
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							else if (spi->tx_buf)/* Load data for discontinuous mode */
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			stm32f4_spi_write_tx(spi);
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								stm32f4_spi_write_tx(spi);
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	}
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						}
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					@ -1151,7 +1153,9 @@ static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi)
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	/* Enable the interrupts relative to the current communication mode */
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						/* Enable the interrupts relative to the current communication mode */
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	if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
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						if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
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		cr2 |= STM32F4_SPI_CR2_TXEIE;
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							cr2 |= STM32F4_SPI_CR2_TXEIE;
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	} else if (spi->cur_comm == SPI_FULL_DUPLEX) {
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						} else if (spi->cur_comm == SPI_FULL_DUPLEX ||
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									spi->cur_comm == SPI_SIMPLEX_RX ||
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									spi->cur_comm == SPI_3WIRE_RX) {
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		/* In transmit-only mode, the OVR flag is set in the SR register
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							/* In transmit-only mode, the OVR flag is set in the SR register
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		 * since the received data are never read. Therefore set OVR
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							 * since the received data are never read. Therefore set OVR
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		 * interrupt only when rx buffer is available.
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							 * interrupt only when rx buffer is available.
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					@ -1462,10 +1466,16 @@ static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
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		stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
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							stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
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					STM32F4_SPI_CR1_BIDIMODE |
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										STM32F4_SPI_CR1_BIDIMODE |
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					STM32F4_SPI_CR1_BIDIOE);
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										STM32F4_SPI_CR1_BIDIOE);
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	} else if (comm_type == SPI_FULL_DUPLEX) {
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						} else if (comm_type == SPI_FULL_DUPLEX ||
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									comm_type == SPI_SIMPLEX_RX) {
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		stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
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							stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
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					STM32F4_SPI_CR1_BIDIMODE |
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										STM32F4_SPI_CR1_BIDIMODE |
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					STM32F4_SPI_CR1_BIDIOE);
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										STM32F4_SPI_CR1_BIDIOE);
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						} else if (comm_type == SPI_3WIRE_RX) {
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							stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
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										STM32F4_SPI_CR1_BIDIMODE);
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							stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
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										STM32F4_SPI_CR1_BIDIOE);
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	} else {
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						} else {
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		return -EINVAL;
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							return -EINVAL;
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	}
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						}
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					@ -1906,6 +1916,7 @@ static int stm32_spi_probe(struct platform_device *pdev)
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	master->prepare_message = stm32_spi_prepare_msg;
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						master->prepare_message = stm32_spi_prepare_msg;
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	master->transfer_one = stm32_spi_transfer_one;
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						master->transfer_one = stm32_spi_transfer_one;
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	master->unprepare_message = stm32_spi_unprepare_msg;
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						master->unprepare_message = stm32_spi_unprepare_msg;
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						master->flags = SPI_MASTER_MUST_TX;
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	spi->dma_tx = dma_request_chan(spi->dev, "tx");
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						spi->dma_tx = dma_request_chan(spi->dev, "tx");
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	if (IS_ERR(spi->dma_tx)) {
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						if (IS_ERR(spi->dma_tx)) {
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