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dt-bindings: arm: Convert CoreSight CPU debug to DT schema
Convert the CoreSight CPU debug binding to DT schema format. Reviewed-by: Leo Yan <leo.yan@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20220603011933.3277315-4-robh@kernel.org Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
This commit is contained in:
Rob Herring
Mathieu Poirier
parent
3c15fddf31
commit
66d052047c
3 changed files with 81 additions and 50 deletions
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: CoreSight CPU Debug Component
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maintainers:
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- Mathieu Poirier <mathieu.poirier@linaro.org>
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- Mike Leach <mike.leach@linaro.org>
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- Leo Yan <leo.yan@linaro.org>
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- Suzuki K Poulose <suzuki.poulose@arm.com>
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description: |
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CoreSight CPU debug component are compliant with the ARMv8 architecture
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reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
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external debug module is mainly used for two modes: self-hosted debug and
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external debug, and it can be accessed from mmio region from Coresight and
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eventually the debug module connects with CPU for debugging. And the debug
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module provides sample-based profiling extension, which can be used to sample
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CPU program counter, secure state and exception level, etc; usually every CPU
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has one dedicated debug module to be connected.
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select:
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properties:
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compatible:
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contains:
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const: arm,coresight-cpu-debug
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required:
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- compatible
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allOf:
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- $ref: /schemas/arm/primecell.yaml#
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properties:
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compatible:
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items:
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- const: arm,coresight-cpu-debug
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- const: arm,primecell
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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maxItems: 1
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cpu:
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description:
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A phandle to the cpu this debug component is bound to.
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$ref: /schemas/types.yaml#/definitions/phandle
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power-domains:
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maxItems: 1
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description:
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A phandle to the debug power domain if the debug logic has its own
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dedicated power domain. CPU idle states may also need to be separately
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constrained to keep CPU cores powered.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- cpu
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unevaluatedProperties: false
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examples:
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- |
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debug@f6590000 {
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compatible = "arm,coresight-cpu-debug", "arm,primecell";
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reg = <0xf6590000 0x1000>;
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clocks = <&sys_ctrl 1>;
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clock-names = "apb_pclk";
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cpu = <&cpu0>;
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};
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...
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@ -1,49 +0,0 @@
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* CoreSight CPU Debug Component:
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CoreSight CPU debug component are compliant with the ARMv8 architecture
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reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
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external debug module is mainly used for two modes: self-hosted debug and
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external debug, and it can be accessed from mmio region from Coresight
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and eventually the debug module connects with CPU for debugging. And the
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debug module provides sample-based profiling extension, which can be used
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to sample CPU program counter, secure state and exception level, etc;
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usually every CPU has one dedicated debug module to be connected.
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Required properties:
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- compatible : should be "arm,coresight-cpu-debug"; supplemented with
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"arm,primecell" since this driver is using the AMBA bus
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interface.
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- reg : physical base address and length of the register set.
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- clocks : the clock associated to this component.
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- clock-names : the name of the clock referenced by the code. Since we are
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using the AMBA framework, the name of the clock providing
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the interconnect should be "apb_pclk" and the clock is
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mandatory. The interface between the debug logic and the
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processor core is clocked by the internal CPU clock, so it
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is enabled with CPU clock by default.
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- cpu : the CPU phandle the debug module is affined to. Do not assume it
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to default to CPU0 if omitted.
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Optional properties:
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- power-domains: a phandle to the debug power domain. We use "power-domains"
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binding to turn on the debug logic if it has own dedicated
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power domain and if necessary to use "cpuidle.off=1" or
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"nohlt" in the kernel command line or sysfs node to
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constrain idle states to ensure registers in the CPU power
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domain are accessible.
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Example:
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debug@f6590000 {
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compatible = "arm,coresight-cpu-debug","arm,primecell";
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reg = <0 0xf6590000 0 0x1000>;
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clocks = <&sys_ctrl HI6220_DAPB_CLK>;
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clock-names = "apb_pclk";
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cpu = <&cpu0>;
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};
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@ -1981,7 +1981,6 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git
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F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*
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F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
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F: Documentation/devicetree/bindings/arm/arm,coresight-*.yaml
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F: Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml
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F: Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml
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