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PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus

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TI keystone is the only Designware driver using .scan_bus(). This
function pointer is the only thing preventing the Designware driver from
using pci_host_probe(). Let's use the pci_ops.add_bus hook instead.

Link: https://lore.kernel.org/r/20200821035420.380495-16-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Rob Herring 2020-08-20 21:53:55 -06:00 committed by Lorenzo Pieralisi
parent 6e8e104d21
commit 6ab15b5e70
1 changed files with 9 additions and 3 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

12
drivers/pci/controller/dwc/pci-keystone.c
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@ -454,15 +454,19 @@ static struct pci_ops ks_child_pcie_ops = {
}; };
/** /**
* ks_pcie_v3_65_scan_bus() - keystone scan_bus post initialization * ks_pcie_v3_65_add_bus() - keystone add_bus post initialization
* *
* This sets BAR0 to enable inbound access for MSI_IRQ register * This sets BAR0 to enable inbound access for MSI_IRQ register
*/ */
static void ks_pcie_v3_65_scan_bus(struct pcie_port *pp) static int ks_pcie_v3_65_add_bus(struct pci_bus *bus)
{ {
struct pcie_port *pp = bus->sysdata;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
if (!pci_is_root_bus(bus))
return 0;
/* Configure and set up BAR0 */ /* Configure and set up BAR0 */
ks_pcie_set_dbi_mode(ks_pcie); ks_pcie_set_dbi_mode(ks_pcie);
@ -477,12 +481,15 @@ static void ks_pcie_v3_65_scan_bus(struct pcie_port *pp)
* be sufficient. Use physical address to avoid any conflicts. * be sufficient. Use physical address to avoid any conflicts.
*/ */
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start); dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
return 0;
} }
static struct pci_ops ks_pcie_ops = { static struct pci_ops ks_pcie_ops = {
.map_bus = dw_pcie_own_conf_map_bus, .map_bus = dw_pcie_own_conf_map_bus,
.read = pci_generic_config_read, .read = pci_generic_config_read,
.write = pci_generic_config_write, .write = pci_generic_config_write,
.add_bus = ks_pcie_v3_65_add_bus,
}; };
/** /**
@ -842,7 +849,6 @@ static int __init ks_pcie_host_init(struct pcie_port *pp)
static const struct dw_pcie_host_ops ks_pcie_host_ops = { static const struct dw_pcie_host_ops ks_pcie_host_ops = {
.host_init = ks_pcie_host_init, .host_init = ks_pcie_host_init,
.msi_host_init = ks_pcie_msi_host_init, .msi_host_init = ks_pcie_msi_host_init,
.scan_bus = ks_pcie_v3_65_scan_bus,
}; };
static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = { static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = {