forked from mirrors/linux
ARM: imx3: Remove imx3 soc_init()
imx31_soc_init() and imx35_soc_init() were only used by i.MX31/35 board files. Since the board files users are gone, it is safe to remove imx3 soc_init() functions. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Fabio Estevam
Shawn Guo
parent
a542fc1816
commit
6c5f05a6cd
2 changed files with 0 additions and 161 deletions
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@ -28,8 +28,6 @@ void mx21_init_irq(void);
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void mx31_init_irq(void);
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void mx31_init_irq(void);
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void mx35_init_irq(void);
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void mx35_init_irq(void);
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void imx21_soc_init(void);
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void imx21_soc_init(void);
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void imx31_soc_init(void);
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void imx35_soc_init(void);
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int mx21_clocks_init(unsigned long lref, unsigned long fref);
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int mx21_clocks_init(unsigned long lref, unsigned long fref);
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int mx27_clocks_init(unsigned long fref);
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int mx27_clocks_init(unsigned long fref);
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int mx31_clocks_init(unsigned long fref);
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int mx31_clocks_init(unsigned long fref);
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@ -71,40 +71,6 @@ static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size,
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return __arm_ioremap_caller(phys_addr, size, mtype, caller);
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return __arm_ioremap_caller(phys_addr, size, mtype, caller);
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}
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}
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static void __init imx3_init_l2x0(void)
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{
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#ifdef CONFIG_CACHE_L2X0
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void __iomem *l2x0_base;
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void __iomem *clkctl_base;
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/*
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* First of all, we must repair broken chip settings. There are some
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* i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
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* misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
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* Workaraound is to setup the correct register setting prior enabling the
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* L2 cache. This should not hurt already working CPUs, as they are using the
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* same value.
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*/
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#define L2_MEM_VAL 0x10
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clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
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if (clkctl_base != NULL) {
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writel(0x00000515, clkctl_base + L2_MEM_VAL);
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iounmap(clkctl_base);
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} else {
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pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
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}
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l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
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if (!l2x0_base) {
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printk(KERN_ERR "remapping L2 cache area failed\n");
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return;
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}
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l2x0_init(l2x0_base, 0x00030024, 0x00000000);
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#endif
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}
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#ifdef CONFIG_SOC_IMX31
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#ifdef CONFIG_SOC_IMX31
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static struct map_desc mx31_io_desc[] __initdata = {
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static struct map_desc mx31_io_desc[] __initdata = {
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imx_map_entry(MX31, X_MEMC, MT_DEVICE),
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imx_map_entry(MX31, X_MEMC, MT_DEVICE),
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@ -145,61 +111,6 @@ void __init mx31_init_irq(void)
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{
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{
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mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
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mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
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}
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}
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static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
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.per_2_per_addr = 1677,
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};
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static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
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.ap_2_ap_addr = 423,
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.ap_2_bp_addr = 829,
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.bp_2_ap_addr = 1029,
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};
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static struct sdma_platform_data imx31_sdma_pdata __initdata = {
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.fw_name = "sdma-imx31-to2.bin",
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.script_addrs = &imx31_to2_sdma_script,
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};
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static const struct resource imx31_audmux_res[] __initconst = {
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DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K),
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};
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static const struct resource imx31_rnga_res[] __initconst = {
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DEFINE_RES_MEM(MX31_RNGA_BASE_ADDR, SZ_16K),
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};
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void __init imx31_soc_init(void)
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{
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int to_version = mx31_revision() >> 4;
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imx3_init_l2x0();
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mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
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mxc_device_init();
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mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
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mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
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mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
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pinctrl_provide_dummies();
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if (to_version == 1) {
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strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
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strlen(imx31_sdma_pdata.fw_name));
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imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
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}
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imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
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imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR));
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imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));
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platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res,
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ARRAY_SIZE(imx31_audmux_res));
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platform_device_register_simple("mxc_rnga", -1, imx31_rnga_res,
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ARRAY_SIZE(imx31_rnga_res));
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}
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#endif /* ifdef CONFIG_SOC_IMX31 */
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#endif /* ifdef CONFIG_SOC_IMX31 */
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#ifdef CONFIG_SOC_IMX35
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#ifdef CONFIG_SOC_IMX35
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@ -239,74 +150,4 @@ void __init mx35_init_irq(void)
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{
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{
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mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
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mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
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}
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}
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static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
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.ap_2_ap_addr = 642,
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.uart_2_mcu_addr = 817,
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.mcu_2_app_addr = 747,
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.uartsh_2_mcu_addr = 1183,
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.per_2_shp_addr = 1033,
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.mcu_2_shp_addr = 961,
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.ata_2_mcu_addr = 1333,
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.mcu_2_ata_addr = 1252,
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.app_2_mcu_addr = 683,
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.shp_2_per_addr = 1111,
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.shp_2_mcu_addr = 892,
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};
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static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
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.ap_2_ap_addr = 729,
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.uart_2_mcu_addr = 904,
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.per_2_app_addr = 1597,
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.mcu_2_app_addr = 834,
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.uartsh_2_mcu_addr = 1270,
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.per_2_shp_addr = 1120,
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.mcu_2_shp_addr = 1048,
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.ata_2_mcu_addr = 1429,
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.mcu_2_ata_addr = 1339,
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.app_2_per_addr = 1531,
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.app_2_mcu_addr = 770,
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.shp_2_per_addr = 1198,
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.shp_2_mcu_addr = 979,
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};
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static struct sdma_platform_data imx35_sdma_pdata __initdata = {
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.fw_name = "sdma-imx35-to2.bin",
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.script_addrs = &imx35_to2_sdma_script,
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};
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static const struct resource imx35_audmux_res[] __initconst = {
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DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K),
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};
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void __init imx35_soc_init(void)
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{
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int to_version = mx35_revision() >> 4;
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imx3_init_l2x0();
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mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
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mxc_device_init();
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mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
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mxc_register_gpio("imx35-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
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mxc_register_gpio("imx35-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
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pinctrl_provide_dummies();
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if (to_version == 1) {
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strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
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strlen(imx35_sdma_pdata.fw_name));
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imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
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}
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imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
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/* Setup AIPS registers */
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imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR));
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imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR));
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/* i.mx35 has the i.mx31 type audmux */
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platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res,
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ARRAY_SIZE(imx35_audmux_res));
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}
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#endif /* ifdef CONFIG_SOC_IMX35 */
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#endif /* ifdef CONFIG_SOC_IMX35 */
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