forked from mirrors/linux
spi: armada-3700: Fix padding when sending not 4-byte aligned data
In 4-byte transfer mode, extra padding/dummy bytes '0xff' would be sent in write operation if TX data is not 4-byte aligned since the SPI data register is always shifted out as whole 4 bytes. Fix this by using the header count feature that allows to transfer 0 to 4 bytes. Use it to actually send the first 1 to 3 bytes of data before the rest of the buffer that will hence be 4-byte aligned. Signed-off-by: Zachary Zhang <zhangzg@marvell.com> Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Zachary Zhang
Mark Brown
parent
747e1f6047
commit
6fd6fd68c9
1 changed files with 41 additions and 94 deletions
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@ -99,11 +99,6 @@
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/* A3700_SPI_IF_TIME_REG */
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#define A3700_SPI_CLK_CAPT_EDGE BIT(7)
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/* Flags and macros for struct a3700_spi */
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#define A3700_INSTR_CNT 1
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#define A3700_ADDR_CNT 3
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#define A3700_DUMMY_CNT 1
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struct a3700_spi {
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struct spi_master *master;
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void __iomem *base;
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@ -117,9 +112,6 @@ struct a3700_spi {
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u8 byte_len;
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u32 wait_mask;
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struct completion done;
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u32 addr_cnt;
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u32 instr_cnt;
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size_t hdr_cnt;
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};
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static u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset)
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@ -449,53 +441,35 @@ static void a3700_spi_set_cs(struct spi_device *spi, bool enable)
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static void a3700_spi_header_set(struct a3700_spi *a3700_spi)
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{
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u32 instr_cnt = 0, addr_cnt = 0, dummy_cnt = 0;
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unsigned int addr_cnt;
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u32 val = 0;
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/* Clear the header registers */
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spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0);
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spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0);
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spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0);
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spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);
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/* Set header counters */
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if (a3700_spi->tx_buf) {
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if (a3700_spi->buf_len <= a3700_spi->instr_cnt) {
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instr_cnt = a3700_spi->buf_len;
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} else if (a3700_spi->buf_len <= (a3700_spi->instr_cnt +
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a3700_spi->addr_cnt)) {
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instr_cnt = a3700_spi->instr_cnt;
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addr_cnt = a3700_spi->buf_len - instr_cnt;
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} else if (a3700_spi->buf_len <= a3700_spi->hdr_cnt) {
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instr_cnt = a3700_spi->instr_cnt;
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addr_cnt = a3700_spi->addr_cnt;
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/* Need to handle the normal write case with 1 byte
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* data
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/*
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* when tx data is not 4 bytes aligned, there will be unexpected
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* bytes out of SPI output register, since it always shifts out
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* as whole 4 bytes. This might cause incorrect transaction with
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* some devices. To avoid that, use SPI header count feature to
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* transfer up to 3 bytes of data first, and then make the rest
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* of data 4-byte aligned.
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*/
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if (!a3700_spi->tx_buf[instr_cnt + addr_cnt])
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dummy_cnt = a3700_spi->buf_len - instr_cnt -
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addr_cnt;
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}
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val |= ((instr_cnt & A3700_SPI_INSTR_CNT_MASK)
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<< A3700_SPI_INSTR_CNT_BIT);
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val |= ((addr_cnt & A3700_SPI_ADDR_CNT_MASK)
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<< A3700_SPI_ADDR_CNT_BIT);
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val |= ((dummy_cnt & A3700_SPI_DUMMY_CNT_MASK)
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<< A3700_SPI_DUMMY_CNT_BIT);
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}
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addr_cnt = a3700_spi->buf_len % 4;
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if (addr_cnt) {
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val = (addr_cnt & A3700_SPI_ADDR_CNT_MASK)
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<< A3700_SPI_ADDR_CNT_BIT;
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spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val);
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/* Update the buffer length to be transferred */
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a3700_spi->buf_len -= (instr_cnt + addr_cnt + dummy_cnt);
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a3700_spi->buf_len -= addr_cnt;
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/* Set Instruction */
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val = 0;
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while (instr_cnt--) {
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val = (val << 8) | a3700_spi->tx_buf[0];
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a3700_spi->tx_buf++;
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}
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spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, val);
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/* Set Address */
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/* transfer 1~3 bytes through address count */
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val = 0;
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while (addr_cnt--) {
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val = (val << 8) | a3700_spi->tx_buf[0];
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@ -503,6 +477,8 @@ static void a3700_spi_header_set(struct a3700_spi *a3700_spi)
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}
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spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val);
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}
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}
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}
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static int a3700_is_wfifo_full(struct a3700_spi *a3700_spi)
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{
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@ -515,35 +491,12 @@ static int a3700_is_wfifo_full(struct a3700_spi *a3700_spi)
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static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi)
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{
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u32 val;
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int i = 0;
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while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) {
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val = 0;
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if (a3700_spi->buf_len >= 4) {
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val = cpu_to_le32(*(u32 *)a3700_spi->tx_buf);
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spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val);
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a3700_spi->buf_len -= 4;
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a3700_spi->tx_buf += 4;
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} else {
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/*
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* If the remained buffer length is less than 4-bytes,
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* we should pad the write buffer with all ones. So that
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* it avoids overwrite the unexpected bytes following
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* the last one.
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*/
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val = GENMASK(31, 0);
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while (a3700_spi->buf_len) {
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val &= ~(0xff << (8 * i));
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val |= *a3700_spi->tx_buf++ << (8 * i);
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i++;
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a3700_spi->buf_len--;
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spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG,
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val);
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}
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break;
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}
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}
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return 0;
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@ -648,9 +601,6 @@ static int a3700_spi_transfer_one(struct spi_master *master,
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a3700_spi->rx_buf = xfer->rx_buf;
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a3700_spi->buf_len = xfer->len;
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/* SPI transfer headers */
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a3700_spi_header_set(a3700_spi);
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if (xfer->tx_buf)
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nbits = xfer->tx_nbits;
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else if (xfer->rx_buf)
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@ -658,6 +608,12 @@ static int a3700_spi_transfer_one(struct spi_master *master,
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a3700_spi_pin_mode_set(a3700_spi, nbits, xfer->rx_buf ? true : false);
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/* Flush the FIFOs */
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a3700_spi_fifo_flush(a3700_spi);
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/* Transfer first bytes of data when buffer is not 4-byte aligned */
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a3700_spi_header_set(a3700_spi);
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if (xfer->rx_buf) {
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/* Set read data length */
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spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG,
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@ -736,17 +692,12 @@ static int a3700_spi_transfer_one(struct spi_master *master,
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dev_err(&spi->dev, "wait wfifo empty timed out\n");
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return -ETIMEDOUT;
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}
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} else {
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/*
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* If the instruction in SPI_INSTR does not require data
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* to be written to the SPI device, wait until SPI_RDY
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* is 1 for the SPI interface to be in idle.
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*/
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}
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if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) {
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dev_err(&spi->dev, "wait xfer ready timed out\n");
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return -ETIMEDOUT;
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}
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}
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
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val |= A3700_SPI_XFER_STOP;
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@ -837,10 +788,6 @@ static int a3700_spi_probe(struct platform_device *pdev)
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memset(spi, 0, sizeof(struct a3700_spi));
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spi->master = master;
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spi->instr_cnt = A3700_INSTR_CNT;
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spi->addr_cnt = A3700_ADDR_CNT;
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spi->hdr_cnt = A3700_INSTR_CNT + A3700_ADDR_CNT +
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A3700_DUMMY_CNT;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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spi->base = devm_ioremap_resource(dev, res);
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