forked from mirrors/linux
		
	spi: spi-qpic: add driver for QCOM SPI NAND flash Interface
This driver implements support for the SPI-NAND mode of QCOM NAND Flash Interface as a SPI-MEM controller with pipelined ECC capability. Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> Link: https://patch.msgid.link/20250224111414.2809669-3-quic_mdalam@quicinc.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
		
							parent
							
								
									fd6bc2ba41
								
							
						
					
					
						commit
						7304d19090
					
				
					 5 changed files with 1652 additions and 0 deletions
				
			
		|  | @ -3,7 +3,11 @@ | ||||||
| nandcore-objs := core.o bbt.o | nandcore-objs := core.o bbt.o | ||||||
| obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o | obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o | ||||||
| obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o | obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o | ||||||
|  | ifeq ($(CONFIG_SPI_QPIC_SNAND),y) | ||||||
|  | obj-$(CONFIG_SPI_QPIC_SNAND) += qpic_common.o | ||||||
|  | else | ||||||
| obj-$(CONFIG_MTD_NAND_QCOM) += qpic_common.o | obj-$(CONFIG_MTD_NAND_QCOM) += qpic_common.o | ||||||
|  | endif | ||||||
| obj-y	+= onenand/ | obj-y	+= onenand/ | ||||||
| obj-y	+= raw/ | obj-y	+= raw/ | ||||||
| obj-y	+= spi/ | obj-y	+= spi/ | ||||||
|  |  | ||||||
|  | @ -936,6 +936,15 @@ config SPI_QCOM_QSPI | ||||||
| 	help | 	help | ||||||
| 	  QSPI(Quad SPI) driver for Qualcomm QSPI controller. | 	  QSPI(Quad SPI) driver for Qualcomm QSPI controller. | ||||||
| 
 | 
 | ||||||
|  | config SPI_QPIC_SNAND | ||||||
|  | 	bool "QPIC SNAND controller" | ||||||
|  | 	depends on ARCH_QCOM || COMPILE_TEST | ||||||
|  | 	select MTD | ||||||
|  | 	help | ||||||
|  | 	  QPIC_SNAND (QPIC SPI NAND) driver for Qualcomm QPIC controller. | ||||||
|  | 	  QPIC controller supports both parallel nand and serial nand. | ||||||
|  | 	  This config will enable serial nand driver for QPIC controller. | ||||||
|  | 
 | ||||||
| config SPI_QUP | config SPI_QUP | ||||||
| 	tristate "Qualcomm SPI controller with QUP interface" | 	tristate "Qualcomm SPI controller with QUP interface" | ||||||
| 	depends on ARCH_QCOM || COMPILE_TEST | 	depends on ARCH_QCOM || COMPILE_TEST | ||||||
|  |  | ||||||
|  | @ -117,6 +117,7 @@ obj-$(CONFIG_SPI_PXA2XX)		+= spi-pxa2xx-platform.o | ||||||
| obj-$(CONFIG_SPI_PXA2XX_PCI)		+= spi-pxa2xx-pci.o | obj-$(CONFIG_SPI_PXA2XX_PCI)		+= spi-pxa2xx-pci.o | ||||||
| obj-$(CONFIG_SPI_QCOM_GENI)		+= spi-geni-qcom.o | obj-$(CONFIG_SPI_QCOM_GENI)		+= spi-geni-qcom.o | ||||||
| obj-$(CONFIG_SPI_QCOM_QSPI)		+= spi-qcom-qspi.o | obj-$(CONFIG_SPI_QCOM_QSPI)		+= spi-qcom-qspi.o | ||||||
|  | obj-$(CONFIG_SPI_QPIC_SNAND)            += spi-qpic-snand.o | ||||||
| obj-$(CONFIG_SPI_QUP)			+= spi-qup.o | obj-$(CONFIG_SPI_QUP)			+= spi-qup.o | ||||||
| obj-$(CONFIG_SPI_ROCKCHIP)		+= spi-rockchip.o | obj-$(CONFIG_SPI_ROCKCHIP)		+= spi-rockchip.o | ||||||
| obj-$(CONFIG_SPI_ROCKCHIP_SFC)		+= spi-rockchip-sfc.o | obj-$(CONFIG_SPI_ROCKCHIP_SFC)		+= spi-rockchip-sfc.o | ||||||
|  |  | ||||||
							
								
								
									
										1631
									
								
								drivers/spi/spi-qpic-snand.c
									
									
									
									
									
										Normal file
									
								
							
							
						
						
									
										1631
									
								
								drivers/spi/spi-qpic-snand.c
									
									
									
									
									
										Normal file
									
								
							
										
											
												File diff suppressed because it is too large
												Load diff
											
										
									
								
							|  | @ -325,6 +325,10 @@ struct nandc_regs { | ||||||
| 	__le32 read_location_last1; | 	__le32 read_location_last1; | ||||||
| 	__le32 read_location_last2; | 	__le32 read_location_last2; | ||||||
| 	__le32 read_location_last3; | 	__le32 read_location_last3; | ||||||
|  | 	__le32 spi_cfg; | ||||||
|  | 	__le32 num_addr_cycle; | ||||||
|  | 	__le32 busy_wait_cnt; | ||||||
|  | 	__le32 flash_feature; | ||||||
| 
 | 
 | ||||||
| 	__le32 erased_cw_detect_cfg_clr; | 	__le32 erased_cw_detect_cfg_clr; | ||||||
| 	__le32 erased_cw_detect_cfg_set; | 	__le32 erased_cw_detect_cfg_set; | ||||||
|  | @ -339,6 +343,7 @@ struct nandc_regs { | ||||||
|  * |  * | ||||||
|  * @core_clk:			controller clock |  * @core_clk:			controller clock | ||||||
|  * @aon_clk:			another controller clock |  * @aon_clk:			another controller clock | ||||||
|  |  * @iomacro_clk:		io macro clock | ||||||
|  * |  * | ||||||
|  * @regs:			a contiguous chunk of memory for DMA register |  * @regs:			a contiguous chunk of memory for DMA register | ||||||
|  *				writes. contains the register values to be |  *				writes. contains the register values to be | ||||||
|  | @ -348,6 +353,7 @@ struct nandc_regs { | ||||||
|  *				initialized via DT match data |  *				initialized via DT match data | ||||||
|  * |  * | ||||||
|  * @controller:			base controller structure |  * @controller:			base controller structure | ||||||
|  |  * @qspi:			qpic spi structure | ||||||
|  * @host_list:			list containing all the chips attached to the |  * @host_list:			list containing all the chips attached to the | ||||||
|  *				controller |  *				controller | ||||||
|  * |  * | ||||||
|  | @ -392,6 +398,7 @@ struct qcom_nand_controller { | ||||||
| 	const struct qcom_nandc_props *props; | 	const struct qcom_nandc_props *props; | ||||||
| 
 | 
 | ||||||
| 	struct nand_controller *controller; | 	struct nand_controller *controller; | ||||||
|  | 	struct qpic_spi_nand *qspi; | ||||||
| 	struct list_head host_list; | 	struct list_head host_list; | ||||||
| 
 | 
 | ||||||
| 	union { | 	union { | ||||||
|  |  | ||||||
		Loading…
	
		Reference in a new issue
	
	 Md Sadre Alam
						Md Sadre Alam