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mn10300: Remove the architecture

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Remove the MN10300 arch as the hardware is defunct.

Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: David Howells <dhowells@redhat.com>
cc: Masahiro Yamada <yamada.masahiro@socionext.com>
cc: linux-am33-list@redhat.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
David Howells 2018-03-08 09:48:46 +00:00 committed by Arnd Bergmann
parent b67aea2bba
commit 739d875dd6
343 changed files with 21 additions and 34163 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

2
Documentation/00-INDEX
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@ -284,8 +284,6 @@ misc-devices/
- directory with info about devices using the misc dev subsystem - directory with info about devices using the misc dev subsystem
mmc/ mmc/
- directory with info about the MMC subsystem - directory with info about the MMC subsystem
mn10300/
- directory with info about the mn10300 architecture port
mtd/ mtd/
- directory with info about memory technology devices (flash) - directory with info about memory technology devices (flash)
namespaces/ namespaces/

1
Documentation/features/core/BPF-JIT/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/core/generic-idle-thread/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | ok | | parisc: | ok |

1
Documentation/features/core/jump-labels/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/core/tracehook/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| mn10300: | ok |
| nios2: | ok | | nios2: | ok |
| openrisc: | ok | | openrisc: | ok |
| parisc: | ok | | parisc: | ok |

1
Documentation/features/debug/KASAN/arch-support.txt
View file

@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/debug/gcov-profile-all/arch-support.txt
View file

@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | ok | | microblaze: | ok |
| mips: | TODO | | mips: | TODO |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/debug/kgdb/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | ok | | microblaze: | ok |
| mips: | ok | | mips: | ok |
| mn10300: | ok |
| nios2: | ok | | nios2: | ok |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/debug/kprobes-on-ftrace/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/debug/kprobes/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/debug/kretprobes/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/debug/optprobes/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/debug/stackprotector/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/debug/uprobes/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/debug/user-ret-profiler/arch-support.txt
View file

@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/io/dma-api-debug/arch-support.txt
View file

@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | ok | | microblaze: | ok |
| mips: | ok | | mips: | ok |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/io/dma-contiguous/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/io/sg-chain/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/lib/strncasecmp/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/locking/cmpxchg-local/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/locking/lockdep/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | ok | | microblaze: | ok |
| mips: | ok | | mips: | ok |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/locking/queued-rwlocks/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/locking/queued-spinlocks/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/locking/rwsem-optimized/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/perf/kprobes-event/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/perf/perf-regs/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/perf/perf-stackdump/arch-support.txt
View file

@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/sched/membarrier-sync-core/arch-support.txt
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@ -44,7 +44,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/sched/numa-balancing/arch-support.txt
View file

@ -21,7 +21,6 @@
| m68k: | .. | | m68k: | .. |
| microblaze: | .. | | microblaze: | .. |
| mips: | TODO | | mips: | TODO |
| mn10300: | .. |
| nios2: | .. | | nios2: | .. |
| openrisc: | .. | | openrisc: | .. |
| parisc: | .. | | parisc: | .. |

1
Documentation/features/seccomp/seccomp-filter/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/time/arch-tick-broadcast/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/time/clockevents/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | ok | | m68k: | ok |
| microblaze: | ok | | microblaze: | ok |
| mips: | ok | | mips: | ok |
| mn10300: | ok |
| nios2: | ok | | nios2: | ok |
| openrisc: | ok | | openrisc: | ok |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/time/context-tracking/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/time/irq-time-acct/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | .. | | parisc: | .. |

1
Documentation/features/time/modern-timekeeping/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | ok | | microblaze: | ok |
| mips: | ok | | mips: | ok |
| mn10300: | ok |
| nios2: | ok | | nios2: | ok |
| openrisc: | ok | | openrisc: | ok |
| parisc: | ok | | parisc: | ok |

1
Documentation/features/time/virt-cpuacct/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | ok | | parisc: | ok |

1
Documentation/features/vm/ELF-ASLR/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/vm/PG_uncached/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/vm/THP/arch-support.txt
View file

@ -21,7 +21,6 @@
| m68k: | .. | | m68k: | .. |
| microblaze: | .. | | microblaze: | .. |
| mips: | ok | | mips: | ok |
| mn10300: | .. |
| nios2: | .. | | nios2: | .. |
| openrisc: | .. | | openrisc: | .. |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/vm/TLB/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | .. | | m68k: | .. |
| microblaze: | .. | | microblaze: | .. |
| mips: | TODO | | mips: | TODO |
| mn10300: | TODO |
| nios2: | .. | | nios2: | .. |
| openrisc: | .. | | openrisc: | .. |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/vm/huge-vmap/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/vm/ioremap_prot/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/vm/numa-memblock/arch-support.txt
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@ -21,7 +21,6 @@
| m68k: | .. | | m68k: | .. |
| microblaze: | ok | | microblaze: | ok |
| mips: | ok | | mips: | ok |
| mn10300: | TODO |
| nios2: | .. | | nios2: | .. |
| openrisc: | .. | | openrisc: | .. |
| parisc: | .. | | parisc: | .. |

1
Documentation/features/vm/pte_special/arch-support.txt
View file

@ -21,7 +21,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| mn10300: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

149
Documentation/mn10300/ABI.txt
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@ -1,149 +0,0 @@
=========================
MN10300 FUNCTION CALL ABI
=========================
=======
GENERAL
=======
The MN10300/AM33 kernel runs in little-endian mode; big-endian mode is not
supported.
The stack grows downwards, and should always be 32-bit aligned. There are
separate stack pointer registers for userspace and the kernel.
================
ARGUMENT PASSING
================
The first two arguments (assuming up to 32-bits per argument) to a function are
passed in the D0 and D1 registers respectively; all other arguments are passed
on the stack.
If 64-bit arguments are being passed, then they are never split between
registers and the stack. If the first argument is a 64-bit value, it will be
passed in D0:D1. If the first argument is not a 64-bit value, but the second
is, the second will be passed entirely on the stack and D1 will be unused.
Arguments smaller than 32-bits are not coalesced within a register or a stack
word. For example, two byte-sized arguments will always be passed in separate
registers or word-sized stack slots.
=================
CALLING FUNCTIONS
=================
The caller must allocate twelve bytes on the stack for the callee's use before
it inserts a CALL instruction. The CALL instruction will write into the TOS
word, but won't actually modify the stack pointer; similarly, the RET
instruction reads from the TOS word of the stack, but doesn't move the stack
pointer beyond it.
Stack:
| |
| |
|---------------| SP+20
| 4th Arg |
|---------------| SP+16
| 3rd Arg |
|---------------| SP+12
| D1 Save Slot |
|---------------| SP+8
| D0 Save Slot |
|---------------| SP+4
| Return Addr |
|---------------| SP
| |
| |
The caller must leave space on the stack (hence an allocation of twelve bytes)
in which the callee may store the first two arguments.
============
RETURN VALUE
============
The return value is passed in D0 for an integer (or D0:D1 for a 64-bit value),
or A0 for a pointer.
If the return value is a value larger than 64-bits, or is a structure or an
array, then a hidden first argument will be passed to the callee by the caller:
this will point to a piece of memory large enough to hold the result of the
function. In this case, the callee will return the value in that piece of
memory, and no value will be returned in D0 or A0.
===================
REGISTER CLOBBERING
===================
The values in certain registers may be clobbered by the callee, and other
values must be saved:
Clobber: D0-D1, A0-A1, E0-E3
Save: D2-D3, A2-A3, E4-E7, SP
All other non-supervisor-only registers are clobberable (such as MDR, MCRL,
MCRH).
=================
SPECIAL REGISTERS
=================
Certain ordinary registers may carry special usage for the compiler:
A3: Frame pointer
E2: TLS pointer
==========
KERNEL ABI
==========
The kernel may use a slightly different ABI internally.
(*) E2
If CONFIG_MN10300_CURRENT_IN_E2 is defined, then the current task pointer
will be kept in the E2 register, and that register will be marked
unavailable for the compiler to use as a scratch register.
Normally the kernel uses something like:
MOV SP,An
AND 0xFFFFE000,An
MOV (An),Rm // Rm holds current
MOV (yyy,Rm) // Access current->yyy
To find the address of current; but since this option permits current to
be carried globally in an register, it can use:
MOV (yyy,E2) // Access current->yyy
instead.
===============
SYSTEM CALL ABI
===============
System calls are called with the following convention:
REGISTER ENTRY EXIT
=============== ======================= =======================
D0 Syscall number Return value
A0 1st syscall argument Saved
D1 2nd syscall argument Saved
A3 3rd syscall argument Saved
A2 4th syscall argument Saved
D3 5th syscall argument Saved
D2 6th syscall argument Saved
All other registers are saved. The layout is a consequence of the way the MOVM
instruction stores registers onto the stack.

60
Documentation/mn10300/compartmentalisation.txt
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@ -1,60 +0,0 @@
=========================================
PART-SPECIFIC SOURCE COMPARTMENTALISATION
=========================================
The sources for various parts are compartmentalised at two different levels:
(1) Processor level
The "processor level" is a CPU core plus the other on-silicon
peripherals.
Processor-specific header files are divided among directories in a similar
way to the CPU level:
(*) include/asm-mn10300/proc-mn103e010/
Support for the AM33v2 CPU core.
The appropriate processor is selected by a CONFIG_MN10300_PROC_YYYY option
from the "Processor support" choice menu in the arch/mn10300/Kconfig file.
(2) Unit level
The "unit level" is a processor plus all the external peripherals
controlled by that processor.
Unit-specific header files are divided among directories in a similar way
to the CPU level; not only that, but specific sources may also be
segregated into separate directories under the arch directory:
(*) include/asm-mn10300/unit-asb2303/
(*) arch/mn10300/unit-asb2303/
Support for the ASB2303 board with an ASB2308 daughter board.
(*) include/asm-mn10300/unit-asb2305/
(*) arch/mn10300/unit-asb2305/
Support for the ASB2305 board.
The appropriate processor is selected by a CONFIG_MN10300_UNIT_ZZZZ option
from the "Unit type" choice menu in the arch/mn10300/Kconfig file.
============
COMPILE TIME
============
When the kernel is compiled, symbolic links will be made in the asm header file
directory for this arch:
include/asm-mn10300/proc => include/asm-mn10300/proc-YYYY/
include/asm-mn10300/unit => include/asm-mn10300/unit-ZZZZ/
So that the header files contained in those directories can be accessed without
lots of #ifdef-age.
The appropriate arch/mn10300/unit-ZZZZ directory will also be entered by the
compilation process; all other unit-specific directories will be ignored.

8
MAINTAINERS
View file

@ -10394,14 +10394,6 @@ L: platform-driver-x86@vger.kernel.org
S: Maintained S: Maintained
F: drivers/platform/x86/panasonic-laptop.c F: drivers/platform/x86/panasonic-laptop.c
PANASONIC MN10300/AM33/AM34 PORT
M: David Howells <dhowells@redhat.com>
L: linux-am33-list@redhat.com (moderated for non-subscribers)
W: ftp://ftp.redhat.com/pub/redhat/gnupro/AM33/
S: Maintained
F: Documentation/mn10300/
F: arch/mn10300/
PARALLEL LCD/KEYPAD PANEL DRIVER PARALLEL LCD/KEYPAD PANEL DRIVER
M: Willy Tarreau <willy@haproxy.com> M: Willy Tarreau <willy@haproxy.com>
M: Ksenija Stanojevic <ksenija.stanojevic@gmail.com> M: Ksenija Stanojevic <ksenija.stanojevic@gmail.com>

499
arch/mn10300/Kconfig
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@ -1,499 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
config MN10300
def_bool y
select HAVE_EXIT_THREAD
select HAVE_OPROFILE
select HAVE_UID16
select GENERIC_IRQ_SHOW
select ARCH_WANT_IPC_PARSE_VERSION
select HAVE_ARCH_TRACEHOOK
select HAVE_ARCH_KGDB
select GENERIC_ATOMIC64
select HAVE_NMI_WATCHDOG if MN10300_WD_TIMER
select VIRT_TO_BUS
select GENERIC_CLOCKEVENTS
select MODULES_USE_ELF_RELA
select OLD_SIGSUSPEND3
select OLD_SIGACTION
select HAVE_DEBUG_STACKOVERFLOW
select ARCH_NO_COHERENT_DMA_MMAP
config AM33_2
def_bool n
config AM33_3
def_bool n
config AM34_2
def_bool n
select MN10300_HAS_ATOMIC_OPS_UNIT
select MN10300_HAS_CACHE_SNOOP
config ERRATUM_NEED_TO_RELOAD_MMUCTR
def_bool y if AM33_3 || AM34_2
config MMU
def_bool y
config HIGHMEM
def_bool n
config NUMA
def_bool n
config RWSEM_GENERIC_SPINLOCK
def_bool y
config RWSEM_XCHGADD_ALGORITHM
bool
config GENERIC_CALIBRATE_DELAY
def_bool y
config GENERIC_HWEIGHT
def_bool y
config GENERIC_BUG
def_bool y
depends on BUG
config QUICKLIST
def_bool y
config ARCH_HAS_ILOG2_U32
def_bool y
config HOTPLUG_CPU
def_bool n
source "init/Kconfig"
source "kernel/Kconfig.freezer"
menu "Panasonic MN10300 system setup"
choice
prompt "Unit type"
default MN10300_UNIT_ASB2303
help
This option specifies board for which the kernel will be
compiled. It affects the external peripherals catered for.
config MN10300_UNIT_ASB2303
bool "ASB2303"
config MN10300_UNIT_ASB2305
bool "ASB2305"
config MN10300_UNIT_ASB2364
bool "ASB2364"
select SMSC911X_ARCH_HOOKS if SMSC911X
endchoice
choice
prompt "Processor support"
default MN10300_PROC_MN103E010
help
This option specifies the processor for which the kernel will be
compiled. It affects the on-chip peripherals catered for.
config MN10300_PROC_MN103E010
bool "MN103E010"
depends on MN10300_UNIT_ASB2303 || MN10300_UNIT_ASB2305
select AM33_2
select MN10300_PROC_HAS_TTYSM0
select MN10300_PROC_HAS_TTYSM1
select MN10300_PROC_HAS_TTYSM2
config MN10300_PROC_MN2WS0050
bool "MN2WS0050"
depends on MN10300_UNIT_ASB2364
select AM34_2
select MN10300_PROC_HAS_TTYSM0
select MN10300_PROC_HAS_TTYSM1
select MN10300_PROC_HAS_TTYSM2
endchoice
config MN10300_HAS_ATOMIC_OPS_UNIT
def_bool n
help
This should be enabled if the processor has an atomic ops unit
capable of doing LL/SC equivalent operations.
config FPU
bool "FPU present"
default y
depends on MN10300_PROC_MN103E010 || MN10300_PROC_MN2WS0050
config LAZY_SAVE_FPU
bool "Save FPU state lazily"
default y
depends on FPU && !SMP
help
Enable this to be lazy in the saving of the FPU state to the owning
task's thread struct. This is useful if most tasks on the system
don't use the FPU as only those tasks that use it will pass it
between them, and the state needn't be saved for a task that isn't
using it.
This can't be so easily used on SMP as the process that owns the FPU
state on a CPU may be currently running on another CPU, so for the
moment, it is disabled.
source "arch/mn10300/mm/Kconfig.cache"
config MN10300_TLB_USE_PIDR
def_bool y
menu "Memory layout options"
config KERNEL_RAM_BASE_ADDRESS
hex "Base address of kernel RAM"
default "0x90000000"
config INTERRUPT_VECTOR_BASE
hex "Base address of vector table"
default "0x90000000"
help
The base address of the vector table will be programmed into
the TBR register. It must be on 16MiB address boundary.
config KERNEL_TEXT_ADDRESS
hex "Base address of kernel"
default "0x90001000"
config KERNEL_ZIMAGE_BASE_ADDRESS
hex "Base address of compressed vmlinux image"
default "0x50700000"
config BOOT_STACK_OFFSET
hex
default "0xF00" if SMP
default "0xFF0" if !SMP
config BOOT_STACK_SIZE
hex
depends on SMP
default "0x100"
endmenu
config SMP
bool "Symmetric multi-processing support"
default y
depends on MN10300_PROC_MN2WS0050
---help---
This enables support for systems with more than one CPU. If you have
a system with only one CPU, say N. If you have a system with more
than one CPU, say Y.
If you say N here, the kernel will run on uni- and multiprocessor
machines, but will use only one CPU of a multiprocessor machine. If
you say Y here, the kernel will run on many, but not all,
uniprocessor machines. On a uniprocessor machine, the kernel
will run faster if you say N here.
See also <file:Documentation/x86/i386/IO-APIC.txt>,
<file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
<http://www.tldp.org/docs.html#howto>.
If you don't know what to do here, say N.
config NR_CPUS
int
depends on SMP
default "2"
source "kernel/Kconfig.preempt"
config MN10300_CURRENT_IN_E2
bool "Hold current task address in E2 register"
depends on !SMP
default y
help
This option removes the E2/R2 register from the set available to gcc
for normal use and instead uses it to store the address of the
current process's task_struct whilst in the kernel.
This means the kernel doesn't need to calculate the address each time
"current" is used (take SP, AND with mask and dereference pointer
just to get the address), and instead can just use E2+offset
addressing each time.
This has no effect on userspace.
config MN10300_USING_JTAG
bool "Using JTAG to debug kernel"
default y
help
This options indicates that JTAG will be used to debug the kernel. It
suppresses the use of certain hardware debugging features, such as
single-stepping, which are taken over completely by the JTAG unit.
source "kernel/Kconfig.hz"
config MN10300_RTC
bool "Using MN10300 RTC"
depends on MN10300_PROC_MN103E010 || MN10300_PROC_MN2WS0050
select RTC_CLASS
select RTC_DRV_CMOS
select RTC_SYSTOHC
default n
help
This option enables support for the RTC, thus enabling time to be
tracked, even when system is powered down. This is available on-chip
on the MN103E010.
config MN10300_WD_TIMER
bool "Using MN10300 watchdog timer"
default y
help
This options indicates that the watchdog timer will be used.
config PCI
bool "Use PCI"
depends on MN10300_UNIT_ASB2305
default y
select GENERIC_PCI_IOMAP
help
Some systems (such as the ASB2305) have PCI onboard. If you have one
of these boards and you wish to use the PCI facilities, say Y here.
The PCI-HOWTO, available from
<http://www.tldp.org/docs.html#howto>, contains valuable
information about which PCI hardware does work under Linux and which
doesn't.
source "drivers/pci/Kconfig"
source "drivers/pcmcia/Kconfig"
menu "MN10300 internal serial options"
config MN10300_PROC_HAS_TTYSM0
bool
default n
config MN10300_PROC_HAS_TTYSM1
bool
default n
config MN10300_PROC_HAS_TTYSM2
bool
default n
config MN10300_TTYSM
bool "Support for ttySM serial ports"
depends on MN10300
default y
select SERIAL_CORE
help
This option enables support for the on-chip serial ports that the
MN10300 has available.
config MN10300_TTYSM_CONSOLE
bool "Support for console on ttySM serial ports"
depends on MN10300_TTYSM
select SERIAL_CORE_CONSOLE
help
This option enables support for a console on the on-chip serial ports
that the MN10300 has available.
#
# /dev/ttySM0
#
config MN10300_TTYSM0
bool "Enable SIF0 (/dev/ttySM0)"
depends on MN10300_TTYSM && MN10300_PROC_HAS_TTYSM0
help
Enable access to SIF0 through /dev/ttySM0 or gdb-stub
choice
prompt "Select the timer to supply the clock for SIF0"
default MN10300_TTYSM0_TIMER8
depends on MN10300_TTYSM0
config MN10300_TTYSM0_TIMER8
bool "Use timer 8 (16-bit)"
config MN10300_TTYSM0_TIMER2
bool "Use timer 2 (8-bit)"
endchoice
#
# /dev/ttySM1
#
config MN10300_TTYSM1
bool "Enable SIF1 (/dev/ttySM1)"
depends on MN10300_TTYSM && MN10300_PROC_HAS_TTYSM1
help
Enable access to SIF1 through /dev/ttySM1 or gdb-stub
choice
prompt "Select the timer to supply the clock for SIF1"
default MN10300_TTYSM1_TIMER12 \
if !(AM33_2 || AM33_3)
default MN10300_TTYSM1_TIMER9 \
if AM33_2 || AM33_3
depends on MN10300_TTYSM1
config MN10300_TTYSM1_TIMER12
bool "Use timer 12 (16-bit)"
depends on !(AM33_2 || AM33_3)
config MN10300_TTYSM1_TIMER9
bool "Use timer 9 (16-bit)"
depends on AM33_2 || AM33_3
config MN10300_TTYSM1_TIMER3
bool "Use timer 3 (8-bit)"
depends on AM33_2 || AM33_3
endchoice
#
# /dev/ttySM2
#
config MN10300_TTYSM2
bool "Enable SIF2 (/dev/ttySM2)"
depends on MN10300_TTYSM && MN10300_PROC_HAS_TTYSM2
help
Enable access to SIF2 through /dev/ttySM2 or gdb-stub
choice
prompt "Select the timer to supply the clock for SIF2"
default MN10300_TTYSM2_TIMER3 \
if !(AM33_2 || AM33_3)
default MN10300_TTYSM2_TIMER10 \
if AM33_2 || AM33_3
depends on MN10300_TTYSM2
config MN10300_TTYSM2_TIMER9
bool "Use timer 9 (16-bit)"
depends on !(AM33_2 || AM33_3)
config MN10300_TTYSM2_TIMER1
bool "Use timer 1 (8-bit)"
depends on !(AM33_2 || AM33_3)
config MN10300_TTYSM2_TIMER3
bool "Use timer 3 (8-bit)"
depends on !(AM33_2 || AM33_3)
config MN10300_TTYSM2_TIMER10
bool "Use timer 10 (16-bit)"
depends on AM33_2 || AM33_3
endchoice
config MN10300_TTYSM2_CTS
bool "Enable the use of the CTS line /dev/ttySM2"
depends on MN10300_TTYSM2 && AM33_2
endmenu
menu "Interrupt request priority options"
comment "[!] NOTE: A lower number/level indicates a higher priority (0 is highest, 6 is lowest)"
comment "____Non-maskable interrupt levels____"
comment "The following must be set to a higher priority than local_irq_disable() and on-chip serial"
config DEBUGGER_IRQ_LEVEL
int "DEBUGGER interrupt priority"
depends on KERNEL_DEBUGGER
range 0 1 if LINUX_CLI_LEVEL = 2
range 0 2 if LINUX_CLI_LEVEL = 3
range 0 3 if LINUX_CLI_LEVEL = 4
range 0 4 if LINUX_CLI_LEVEL = 5
range 0 5 if LINUX_CLI_LEVEL = 6
default 0
comment "The following must be set to a higher priority than local_irq_disable()"
config MN10300_SERIAL_IRQ_LEVEL
int "MN10300 on-chip serial interrupt priority"
depends on MN10300_TTYSM
range 1 1 if LINUX_CLI_LEVEL = 2
range 1 2 if LINUX_CLI_LEVEL = 3
range 1 3 if LINUX_CLI_LEVEL = 4
range 1 4 if LINUX_CLI_LEVEL = 5
range 1 5 if LINUX_CLI_LEVEL = 6
default 1
comment "-"
comment "____Maskable interrupt levels____"
config LINUX_CLI_LEVEL
int "The highest interrupt priority excluded by local_irq_disable() (2-6)"
range 2 6
default 2
help
local_irq_disable() doesn't actually disable maskable interrupts -
what it does is restrict the levels of interrupt which are permitted
(a lower level indicates a higher priority) by lowering the value in
EPSW.IM from 7. Any interrupt is permitted for which the level is
lower than EPSW.IM.
Certain interrupts, such as DEBUGGER and virtual MN10300 on-chip
serial DMA interrupts are allowed to interrupt normal disabled
sections.
comment "The following must be set to a equal to or lower priority than LINUX_CLI_LEVEL"
config TIMER_IRQ_LEVEL
int "Kernel timer interrupt priority"
range LINUX_CLI_LEVEL 6
default 4
config PCI_IRQ_LEVEL
int "PCI interrupt priority"
depends on PCI
range LINUX_CLI_LEVEL 6
default 5
config ETHERNET_IRQ_LEVEL
int "Ethernet interrupt priority"
depends on SMC91X || SMC911X || SMSC911X
range LINUX_CLI_LEVEL 6
default 6
config EXT_SERIAL_IRQ_LEVEL
int "External serial port interrupt priority"
depends on SERIAL_8250
range LINUX_CLI_LEVEL 6
default 6
endmenu
source "mm/Kconfig"
menu "Power management options"
source kernel/power/Kconfig
endmenu
endmenu
menu "Executable formats"
source "fs/Kconfig.binfmt"
endmenu
source "net/Kconfig"
source "drivers/Kconfig"
source "fs/Kconfig"
source "arch/mn10300/Kconfig.debug"
source "security/Kconfig"
source "crypto/Kconfig"
source "lib/Kconfig"

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@ -1,156 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
menu "Kernel hacking"
source "lib/Kconfig.debug"
config DEBUG_DECOMPRESS_KERNEL
bool "Using serial port during decompressing kernel"
depends on DEBUG_KERNEL
default n
help
If you say Y here you will confirm the start and the end of
decompressing Linux seeing "Uncompressing Linux... " and
"Ok, booting the kernel.\n" on console.
config TEST_MISALIGNMENT_HANDLER
bool "Run tests on the misalignment handler"
depends on DEBUG_KERNEL
default n
help
If you say Y here the kernel will execute a list of misaligned memory
accesses to make sure the misalignment handler deals them with
correctly. If it does not, the kernel will throw a BUG.
config KPROBES
bool "Kprobes"
depends on DEBUG_KERNEL
help
Kprobes allows you to trap at almost any kernel address and
execute a callback function. register_kprobe() establishes
a probepoint and specifies the callback. Kprobes is useful
for kernel debugging, non-intrusive instrumentation and testing.
If in doubt, say "N".
config GDBSTUB
bool "Remote GDB kernel debugging"
depends on DEBUG_KERNEL && DEPRECATED
select DEBUG_INFO
select FRAME_POINTER
help
If you say Y here, it will be possible to remotely debug the kernel
using gdb. This enlarges your kernel ELF image disk size by several
megabytes and requires a machine with more than 16 MB, better 32 MB
RAM to avoid excessive linking time. This is only useful for kernel
hackers. If unsure, say N.
This is deprecated in favour of KGDB and will be removed in a later
version.
config GDBSTUB_IMMEDIATE
bool "Break into GDB stub immediately"
depends on GDBSTUB
help
If you say Y here, GDB stub will break into the program as soon as
possible, leaving the program counter at the beginning of
start_kernel() in init/main.c.
config GDBSTUB_ALLOW_SINGLE_STEP
bool "Allow software single-stepping in GDB stub"
depends on GDBSTUB && !SMP && !PREEMPT
help
Allow GDB stub to perform software single-stepping through the
kernel. This doesn't work very well on SMP or preemptible kernels as
it uses temporary breakpoints to emulate single-stepping.
config GDB_CONSOLE
bool "Console output to GDB"
depends on GDBSTUB
help
If you are using GDB for remote debugging over a serial port and
would like kernel messages to be formatted into GDB $O packets so
that GDB prints them as program output, say 'Y'.
config GDBSTUB_DEBUGGING
bool "Debug GDB stub by messages to serial port"
depends on GDBSTUB
help
This causes debugging messages to be displayed at various points
during execution of the GDB stub routines. Such messages will be
displayed on ttyS0 if that isn't the GDB stub's port, or ttySM0
otherwise.
config GDBSTUB_DEBUG_ENTRY
bool "Debug GDB stub entry"
depends on GDBSTUB_DEBUGGING
help
This option causes information to be displayed about entry to or exit
from the main GDB stub routine.
config GDBSTUB_DEBUG_PROTOCOL
bool "Debug GDB stub protocol"
depends on GDBSTUB_DEBUGGING
help
This option causes information to be displayed about the GDB remote
protocol messages generated exchanged with GDB.
config GDBSTUB_DEBUG_IO
bool "Debug GDB stub I/O"
depends on GDBSTUB_DEBUGGING
help
This option causes information to be displayed about GDB stub's
low-level I/O.
config GDBSTUB_DEBUG_BREAKPOINT
bool "Debug GDB stub breakpoint management"
depends on GDBSTUB_DEBUGGING
help
This option causes information to be displayed about GDB stub's
breakpoint management.
choice
prompt "GDB stub port"
default GDBSTUB_ON_TTYSM0
depends on GDBSTUB
help
Select the serial port used for GDB-stub.
config GDBSTUB_ON_TTYSM0
bool "/dev/ttySM0 [SIF0]"
depends on MN10300_TTYSM0
select GDBSTUB_ON_TTYSMx
config GDBSTUB_ON_TTYSM1
bool "/dev/ttySM1 [SIF1]"
depends on MN10300_TTYSM1
select GDBSTUB_ON_TTYSMx
config GDBSTUB_ON_TTYSM2
bool "/dev/ttySM2 [SIF2]"
depends on MN10300_TTYSM2
select GDBSTUB_ON_TTYSMx
config GDBSTUB_ON_TTYS0
bool "/dev/ttyS0"
select GDBSTUB_ON_TTYSx
config GDBSTUB_ON_TTYS1
bool "/dev/ttyS1"
select GDBSTUB_ON_TTYSx
endchoice
config GDBSTUB_ON_TTYSMx
bool
depends on GDBSTUB_ON_TTYSM0 || GDBSTUB_ON_TTYSM1 || GDBSTUB_ON_TTYSM2
default y
config GDBSTUB_ON_TTYSx
bool
depends on GDBSTUB_ON_TTYS0 || GDBSTUB_ON_TTYS1
default y
endmenu
config KERNEL_DEBUGGER
def_bool y
depends on GDBSTUB || KGDB

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arch/mn10300/Makefile
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@ -1,99 +0,0 @@
###############################################################################
#
# MN10300 Kernel makefile system specifications
#
# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
# Modified by David Howells (dhowells@redhat.com)
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public Licence
# as published by the Free Software Foundation; either version
# 2 of the Licence, or (at your option) any later version.
#
###############################################################################
KBUILD_DEFCONFIG := asb2303_defconfig
CCSPECS := $(shell $(CC) -v 2>&1 | grep "^Reading specs from " | head -1 | cut -c20-)
CCDIR := $(strip $(patsubst %/specs,%,$(CCSPECS)))
KBUILD_CPPFLAGS += -nostdinc -I$(CCDIR)/include
LDFLAGS :=
OBJCOPYFLAGS := -O binary -R .note -R .comment -R .GCC-command-line -R .note.gnu.build-id -S
#LDFLAGS_vmlinux := -Map linkmap.txt
CHECKFLAGS +=
PROCESSOR := unset
UNIT := unset
KBUILD_CFLAGS += -mam33 -DCPU=AM33 $(call cc-option,-mmem-funcs,)
KBUILD_AFLAGS += -mam33 -DCPU=AM33
ifeq ($(CONFIG_MN10300_CURRENT_IN_E2),y)
KBUILD_CFLAGS += -ffixed-e2 -fcall-saved-e5
endif
ifeq ($(CONFIG_MN10300_PROC_MN103E010),y)
PROCESSOR := mn103e010
endif
ifeq ($(CONFIG_MN10300_PROC_MN2WS0050),y)
PROCESSOR := mn2ws0050
endif
ifeq ($(CONFIG_MN10300_UNIT_ASB2303),y)
UNIT := asb2303
endif
ifeq ($(CONFIG_MN10300_UNIT_ASB2305),y)
UNIT := asb2305
endif
ifeq ($(CONFIG_MN10300_UNIT_ASB2364),y)
UNIT := asb2364
endif
head-y := arch/mn10300/kernel/head.o
core-y += arch/mn10300/kernel/ arch/mn10300/mm/
ifneq ($(PROCESSOR),unset)
core-y += arch/mn10300/proc-$(PROCESSOR)/
endif
ifneq ($(UNIT),unset)
core-y += arch/mn10300/unit-$(UNIT)/
endif
libs-y += arch/mn10300/lib/
drivers-$(CONFIG_OPROFILE) += arch/mn10300/oprofile/
boot := arch/mn10300/boot
.PHONY: zImage
KBUILD_IMAGE := $(boot)/zImage
CLEAN_FILES += $(boot)/zImage
CLEAN_FILES += $(boot)/compressed/vmlinux
CLEAN_FILES += $(boot)/compressed/vmlinux.bin
CLEAN_FILES += $(boot)/compressed/vmlinux.bin.gz
zImage: vmlinux
$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
all: zImage
bootstrap:
$(Q)$(MAKEBOOT) bootstrap
archclean:
$(Q)$(MAKE) $(clean)=arch/mn10300/proc-mn103e010
$(Q)$(MAKE) $(clean)=arch/mn10300/unit-asb2303
$(Q)$(MAKE) $(clean)=arch/mn10300/unit-asb2305
define archhelp
echo '* zImage - Compressed kernel image (arch/$(ARCH)/boot/zImage)'
endef
#
# include the appropriate processor- and unit-specific headers
#
KBUILD_CPPFLAGS += -I$(srctree)/arch/mn10300/proc-$(PROCESSOR)/include
KBUILD_CPPFLAGS += -I$(srctree)/arch/mn10300/unit-$(UNIT)/include

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zImage

28
arch/mn10300/boot/Makefile
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@ -1,28 +0,0 @@
# MN10300 kernel compressor and wrapper
#
# Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
# Written by David Howells (dhowells@redhat.com)
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public Licence
# as published by the Free Software Foundation; either version
# 2 of the Licence, or (at your option) any later version.
#
targets := vmlinux.bin zImage
subdir- := compressed
# ---------------------------------------------------------------------------
$(obj)/zImage: $(obj)/compressed/vmlinux FORCE
$(call if_changed,objcopy)
@echo 'Kernel: $@ is ready'
$(obj)/vmlinux.bin: $(obj)/compressed/vmlinux FORCE
$(call if_changed,objcopy)
$(obj)/compressed/vmlinux: FORCE
$(Q)$(MAKE) $(build)=$(obj)/compressed IMAGE_OFFSET=$(IMAGE_OFFSET) $@

22
arch/mn10300/boot/compressed/Makefile
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@ -1,22 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
#
# Create a compressed vmlinux image from the original vmlinux
#
targets := vmlinux vmlinux.bin vmlinux.bin.gz head.o misc.o piggy.o
LDFLAGS_vmlinux := -Ttext $(CONFIG_KERNEL_ZIMAGE_BASE_ADDRESS) -e startup_32
$(obj)/vmlinux: $(obj)/head.o $(obj)/misc.o $(obj)/piggy.o FORCE
$(call if_changed,ld)
$(obj)/vmlinux.bin: vmlinux FORCE
$(call if_changed,objcopy)
$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
$(call if_changed,gzip)
LDFLAGS_piggy.o := -r --format binary --oformat elf32-am33lin -T
$(obj)/piggy.o: $(obj)/vmlinux.lds $(obj)/vmlinux.bin.gz FORCE
$(call if_changed,ld)

151
arch/mn10300/boot/compressed/head.S
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@ -1,151 +0,0 @@
/* Boot entry point for a compressed MN10300 kernel
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
.section .text
#define DEBUG
#include <linux/linkage.h>
#include <asm/cpu-regs.h>
#include <asm/cache.h>
#ifdef CONFIG_SMP
#include <proc/smp-regs.h>
#endif
.globl startup_32
startup_32:
#ifdef CONFIG_SMP
#
# Secondary CPUs jump directly to the kernel entry point
#
# Must save primary CPU's D0-D2 registers as they hold boot parameters
#
mov (CPUID), d3
and CPUID_MASK,d3
beq startup_primary
mov CONFIG_KERNEL_TEXT_ADDRESS,a0
jmp (a0)
startup_primary:
#endif /* CONFIG_SMP */
# first save parameters from bootloader
mov param_save_area,a0
mov d0,(a0)
mov d1,(4,a0)
mov d2,(8,a0)
mov sp,a3
mov decomp_stack+0x2000-4,a0
mov a0,sp
# invalidate and enable both of the caches
mov CHCTR,a0
clr d0
movhu d0,(a0) # turn off first
mov CHCTR_ICINV|CHCTR_DCINV,d0
movhu d0,(a0)
setlb
mov (a0),d0
btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy
lne
#ifdef CONFIG_MN10300_CACHE_ENABLED
#ifdef CONFIG_MN10300_CACHE_WBACK
mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK,d0
#else
mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRTHROUGH,d0
#endif /* WBACK */
movhu d0,(a0) # enable
#endif /* !ENABLED */
# clear the BSS area
mov __bss_start,a0
mov _end,a1
clr d0
bssclear:
cmp a1,a0
bge bssclear_end
movbu d0,(a0)
inc a0
bra bssclear
bssclear_end:
# decompress the kernel
call decompress_kernel[],0
#ifdef CONFIG_MN10300_CACHE_WBACK
call mn10300_dcache_flush_inv[],0
#endif
# disable caches again
mov CHCTR,a0
clr d0
movhu d0,(a0)
setlb
mov (a0),d0
btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy
lne
mov param_save_area,a0
mov (a0),d0
mov (4,a0),d1
mov (8,a0),d2
# jump to the kernel proper entry point
mov a3,sp
mov CONFIG_KERNEL_TEXT_ADDRESS,a0
jmp (a0)
###############################################################################
#
# Cache flush routines
#
###############################################################################
#ifdef CONFIG_MN10300_CACHE_WBACK
mn10300_dcache_flush_inv:
movhu (CHCTR),d0
btst CHCTR_DCEN,d0
beq mn10300_dcache_flush_inv_end
mov L1_CACHE_NENTRIES,d1
clr a1
mn10300_dcache_flush_inv_loop:
mov (DCACHE_PURGE_WAY0(0),a1),d0 # unconditional purge
mov (DCACHE_PURGE_WAY1(0),a1),d0 # unconditional purge
mov (DCACHE_PURGE_WAY2(0),a1),d0 # unconditional purge
mov (DCACHE_PURGE_WAY3(0),a1),d0 # unconditional purge
add L1_CACHE_BYTES,a1
add -1,d1
bne mn10300_dcache_flush_inv_loop
mn10300_dcache_flush_inv_end:
ret [],0
#endif /* CONFIG_MN10300_CACHE_WBACK */
###############################################################################
#
# Data areas
#
###############################################################################
.data
.align 4
param_save_area:
.rept 3
.word 0
.endr
.section .bss
.align 4
decomp_stack:
.space 0x2000

393
arch/mn10300/boot/compressed/misc.c
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@ -1,393 +0,0 @@
/* MN10300 Miscellaneous helper routines for kernel decompressor
*
* Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Modified by David Howells (dhowells@redhat.com)
* - Derived from arch/x86/boot/compressed/misc_32.c
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#include <linux/compiler.h>
#include <asm/serial-regs.h>
#include "misc.h"
#ifndef CONFIG_GDBSTUB_ON_TTYSx
/* display 'Uncompressing Linux... ' messages on ttyS0 or ttyS1 */
#if 1 /* ttyS0 */
#define CYG_DEV_BASE 0xA6FB0000
#else /* ttyS1 */
#define CYG_DEV_BASE 0xA6FC0000
#endif
#define CYG_DEV_THR (*((volatile __u8*)(CYG_DEV_BASE + 0x00)))
#define CYG_DEV_MCR (*((volatile __u8*)(CYG_DEV_BASE + 0x10)))
#define SIO_MCR_DTR 0x01
#define SIO_MCR_RTS 0x02
#define CYG_DEV_LSR (*((volatile __u8*)(CYG_DEV_BASE + 0x14)))
#define SIO_LSR_THRE 0x20 /* transmitter holding register empty */
#define SIO_LSR_TEMT 0x40 /* transmitter register empty */
#define CYG_DEV_MSR (*((volatile __u8*)(CYG_DEV_BASE + 0x18)))
#define SIO_MSR_CTS 0x10 /* clear to send */
#define SIO_MSR_DSR 0x20 /* data set ready */
#define LSR_WAIT_FOR(STATE) \
do { while (!(CYG_DEV_LSR & SIO_LSR_##STATE)) {} } while (0)
#define FLOWCTL_QUERY(LINE) \
({ CYG_DEV_MSR & SIO_MSR_##LINE; })
#define FLOWCTL_WAIT_FOR(LINE) \
do { while (!(CYG_DEV_MSR & SIO_MSR_##LINE)) {} } while (0)
#define FLOWCTL_CLEAR(LINE) \
do { CYG_DEV_MCR &= ~SIO_MCR_##LINE; } while (0)
#define FLOWCTL_SET(LINE) \
do { CYG_DEV_MCR |= SIO_MCR_##LINE; } while (0)
#endif
/*
* gzip declarations
*/
#define OF(args) args
#define STATIC static
#undef memset
#undef memcpy
static inline void *memset(const void *s, int c, size_t n)
{
int i;
char *ss = (char *) s;
for (i = 0; i < n; i++)
ss[i] = c;
return (void *)s;
}
#define memzero(s, n) memset((s), 0, (n))
static inline void *memcpy(void *__dest, const void *__src, size_t __n)
{
int i;
const char *s = __src;
char *d = __dest;
for (i = 0; i < __n; i++)
d[i] = s[i];
return __dest;
}
typedef unsigned char uch;
typedef unsigned short ush;
typedef unsigned long ulg;
#define WSIZE 0x8000 /* Window size must be at least 32k, and a power of
* two */
static uch *inbuf; /* input buffer */
static uch window[WSIZE]; /* sliding window buffer */
static unsigned insize; /* valid bytes in inbuf */
static unsigned inptr; /* index of next byte to be processed in inbuf */
static unsigned outcnt; /* bytes in output buffer */
/* gzip flag byte */
#define ASCII_FLAG 0x01 /* bit 0 set: file probably ASCII text */
#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */
#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */
#define ORIG_NAME 0x08 /* bit 3 set: original file name present */
#define COMMENT 0x10 /* bit 4 set: file comment present */
#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */
#define RESERVED 0xC0 /* bit 6,7: reserved */
/* Diagnostic functions */
#ifdef DEBUG
# define Assert(cond, msg) { if (!(cond)) error(msg); }
# define Trace(x) fprintf x
# define Tracev(x) { if (verbose) fprintf x ; }
# define Tracevv(x) { if (verbose > 1) fprintf x ; }
# define Tracec(c, x) { if (verbose && (c)) fprintf x ; }
# define Tracecv(c, x) { if (verbose > 1 && (c)) fprintf x ; }
#else
# define Assert(cond, msg)
# define Trace(x)
# define Tracev(x)
# define Tracevv(x)
# define Tracec(c, x)
# define Tracecv(c, x)
#endif
static int fill_inbuf(void);
static void flush_window(void);
static void error(const char *) __attribute__((noreturn));
static void kputs(const char *);
static inline unsigned char get_byte(void)
{
unsigned char ch = inptr < insize ? inbuf[inptr++] : fill_inbuf();
#if 0
char hex[3];
hex[0] = ((ch & 0x0f) > 9) ?
((ch & 0x0f) + 'A' - 0xa) : ((ch & 0x0f) + '0');
hex[1] = ((ch >> 4) > 9) ?
((ch >> 4) + 'A' - 0xa) : ((ch >> 4) + '0');
hex[2] = 0;
kputs(hex);
#endif
return ch;
}
/*
* This is set up by the setup-routine at boot-time
*/
#define EXT_MEM_K (*(unsigned short *)0x90002)
#ifndef STANDARD_MEMORY_BIOS_CALL
#define ALT_MEM_K (*(unsigned long *) 0x901e0)
#endif
#define SCREEN_INFO (*(struct screen_info *)0x90000)
static long bytes_out;
static uch *output_data;
static unsigned long output_ptr;
static unsigned long free_mem_ptr = (unsigned long) &end;
static unsigned long free_mem_end_ptr = (unsigned long) &end + 0x90000;
#define INPLACE_MOVE_ROUTINE 0x1000
#define LOW_BUFFER_START 0x2000
#define LOW_BUFFER_END 0x90000
#define LOW_BUFFER_SIZE (LOW_BUFFER_END - LOW_BUFFER_START)
#define HEAP_SIZE 0x3000
static int high_loaded;
static uch *high_buffer_start /* = (uch *)(((ulg)&end) + HEAP_SIZE)*/;
static char *vidmem = (char *)0xb8000;
static int lines, cols;
#define BOOTLOADER_INFLATE
#include "../../../../lib/inflate.c"
static inline void scroll(void)
{
int i;
memcpy(vidmem, vidmem + cols * 2, (lines - 1) * cols * 2);
for (i = (lines - 1) * cols * 2; i < lines * cols * 2; i += 2)
vidmem[i] = ' ';
}
static inline void kputchar(unsigned char ch)
{
#ifdef CONFIG_MN10300_UNIT_ASB2305
while (SC0STR & SC01STR_TBF)
continue;
if (ch == 0x0a) {
SC0TXB = 0x0d;
while (SC0STR & SC01STR_TBF)
continue;
}
SC0TXB = ch;
#else
while (SC1STR & SC01STR_TBF)
continue;
if (ch == 0x0a) {
SC1TXB = 0x0d;
while (SC1STR & SC01STR_TBF)
continue;
}
SC1TXB = ch;
#endif
}
static void kputs(const char *s)
{
#ifdef CONFIG_DEBUG_DECOMPRESS_KERNEL
#ifndef CONFIG_GDBSTUB_ON_TTYSx
char ch;
FLOWCTL_SET(DTR);
while (*s) {
LSR_WAIT_FOR(THRE);
ch = *s++;
if (ch == 0x0a) {
CYG_DEV_THR = 0x0d;
LSR_WAIT_FOR(THRE);
}
CYG_DEV_THR = ch;
}
FLOWCTL_CLEAR(DTR);
#else
for (; *s; s++)
kputchar(*s);
#endif
#endif /* CONFIG_DEBUG_DECOMPRESS_KERNEL */
}
/* ===========================================================================
* Fill the input buffer. This is called only when the buffer is empty
* and at least one byte is really needed.
*/
static int fill_inbuf()
{
if (insize != 0)
error("ran out of input data\n");
inbuf = input_data;
insize = input_len;
inptr = 1;
return inbuf[0];
}
/* ===========================================================================
* Write the output window window[0..outcnt-1] and update crc and bytes_out.
* (Used for the decompressed data only.)
*/
static void flush_window_low(void)
{
ulg c = crc; /* temporary variable */
unsigned n;
uch *in, *out, ch;
in = window;
out = &output_data[output_ptr];
for (n = 0; n < outcnt; n++) {
ch = *out++ = *in++;
c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8);
}
crc = c;
bytes_out += (ulg)outcnt;
output_ptr += (ulg)outcnt;
outcnt = 0;
}
static void flush_window_high(void)
{
ulg c = crc; /* temporary variable */
unsigned n;
uch *in, ch;
in = window;
for (n = 0; n < outcnt; n++) {
ch = *output_data++ = *in++;
if ((ulg) output_data == LOW_BUFFER_END)
output_data = high_buffer_start;
c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8);
}
crc = c;
bytes_out += (ulg)outcnt;
outcnt = 0;
}
static void flush_window(void)
{
if (high_loaded)
flush_window_high();
else
flush_window_low();
}
static void error(const char *x)
{
kputs("\n\n");
kputs(x);
kputs("\n\n -- System halted");
while (1)
/* Halt */;
}
#define STACK_SIZE (4096)
long user_stack[STACK_SIZE];
struct {
long *a;
short b;
} stack_start = { &user_stack[STACK_SIZE], 0 };
void setup_normal_output_buffer(void)
{
#ifdef STANDARD_MEMORY_BIOS_CALL
if (EXT_MEM_K < 1024)
error("Less than 2MB of memory.\n");
#else
if ((ALT_MEM_K > EXT_MEM_K ? ALT_MEM_K : EXT_MEM_K) < 1024)
error("Less than 2MB of memory.\n");
#endif
output_data = (char *) 0x100000; /* Points to 1M */
}
struct moveparams {
uch *low_buffer_start;
int lcount;
uch *high_buffer_start;
int hcount;
};
void setup_output_buffer_if_we_run_high(struct moveparams *mv)
{
high_buffer_start = (uch *)(((ulg) &end) + HEAP_SIZE);
#ifdef STANDARD_MEMORY_BIOS_CALL
if (EXT_MEM_K < (3 * 1024))
error("Less than 4MB of memory.\n");
#else
if ((ALT_MEM_K > EXT_MEM_K ? ALT_MEM_K : EXT_MEM_K) < (3 * 1024))
error("Less than 4MB of memory.\n");
#endif
mv->low_buffer_start = output_data = (char *) LOW_BUFFER_START;
high_loaded = 1;
free_mem_end_ptr = (long) high_buffer_start;
if (0x100000 + LOW_BUFFER_SIZE > (ulg) high_buffer_start) {
high_buffer_start = (uch *)(0x100000 + LOW_BUFFER_SIZE);
mv->hcount = 0; /* say: we need not to move high_buffer */
} else {
mv->hcount = -1;
}
mv->high_buffer_start = high_buffer_start;
}
void close_output_buffer_if_we_run_high(struct moveparams *mv)
{
mv->lcount = bytes_out;
if (bytes_out > LOW_BUFFER_SIZE) {
mv->lcount = LOW_BUFFER_SIZE;
if (mv->hcount)
mv->hcount = bytes_out - LOW_BUFFER_SIZE;
} else {
mv->hcount = 0;
}
}
#undef DEBUGFLAG
#ifdef DEBUGFLAG
int debugflag;
#endif
int decompress_kernel(struct moveparams *mv)
{
#ifdef DEBUGFLAG
while (!debugflag)
barrier();
#endif
output_data = (char *) CONFIG_KERNEL_TEXT_ADDRESS;
makecrc();
kputs("Uncompressing Linux... ");
gunzip();
kputs("Ok, booting the kernel.\n");
return 0;
}

18
arch/mn10300/boot/compressed/misc.h
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@ -1,18 +0,0 @@
/* Internal definitions for the MN10300 kernel decompressor
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
extern int end;
/*
* vmlinux.lds
*/
extern char input_data[];
extern int input_len;

9
arch/mn10300/boot/compressed/vmlinux.lds
View file

@ -1,9 +0,0 @@
SECTIONS
{
.data : {
input_len = .;
LONG(input_data_end - input_data) input_data = .;
*(.data)
input_data_end = .;
}
}

67
arch/mn10300/boot/install.sh
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@ -1,67 +0,0 @@
#!/bin/sh
#
# arch/mn10300/boot/install -c.sh
#
# This file is subject to the terms and conditions of the GNU General Public
# Licence. See the file "COPYING" in the main directory of this archive
# for more details.
#
# Copyright (C) 1995 by Linus Torvalds
#
# Adapted from code in arch/i386/boot/Makefile by H. Peter Anvin
#
# "make install -c" script for i386 architecture
#
# Arguments:
# $1 - kernel version
# $2 - kernel image file
# $3 - kernel map file
# $4 - default install -c path (blank if root directory)
# $5 - boot rom file
#
# User may have a custom install -c script
rm -fr $4/../usr/include/linux $4/../usr/include/asm
install -c -m 0755 $2 $4/vmlinuz
install -c -m 0755 $5 $4/boot.rom
install -c -m 0755 -d $4/../usr/include/linux
cd ${srctree}/include/linux
for i in `find . -maxdepth 1 -name '*.h' -print`; do
install -c -m 0644 $i $4/../usr/include/linux
done
install -c -m 0755 -d $4/../usr/include/linux/byteorder
cd ${srctree}/include/linux/byteorder
for i in `find . -name '*.h' -print`; do
install -c -m 0644 $i $4/../usr/include/linux/byteorder
done
install -c -m 0755 -d $4/../usr/include/linux/lockd
cd ${srctree}/include/linux/lockd
for i in `find . -name '*.h' -print`; do
install -c -m 0644 $i $4/../usr/include/linux/lockd
done
install -c -m 0755 -d $4/../usr/include/linux/netfilter_ipv4
cd ${srctree}/include/linux/netfilter_ipv4
for i in `find . -name '*.h' -print`; do
install -c -m 0644 $i $4/../usr/include/linux/netfilter_ipv4
done
install -c -m 0755 -d $4/../usr/include/linux/nfsd
cd ${srctree}/include/linux/nfsd
for i in `find . -name '*.h' -print`; do
install -c -m 0644 $i $4/../usr/include/linux/nfsd/$i
done
install -c -m 0755 -d $4/../usr/include/linux/raid
cd ${srctree}/include/linux/raid
for i in `find . -name '*.h' -print`; do
install -c -m 0644 $i $4/../usr/include/linux/raid
done
install -c -m 0755 -d $4/../usr/include/linux/sunrpc
cd ${srctree}/include/linux/sunrpc
for i in `find . -name '*.h' -print`; do
install -c -m 0644 $i $4/../usr/include/linux/sunrpc
done
install -c -m 0755 -d $4/../usr/include/asm
cd ${srctree}/include/asm
for i in `find . -name '*.h' -print`; do
install -c -m 0644 $i $4/../usr/include/asm
done

191
arch/mn10300/boot/tools/build.c
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@ -1,191 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 1991, 1992 Linus Torvalds
* Copyright (C) 1997 Martin Mares
*/
/*
* This file builds a disk-image from three different files:
*
* - bootsect: exactly 512 bytes of 8086 machine code, loads the rest
* - setup: 8086 machine code, sets up system parm
* - system: 80386 code for actual system
*
* It does some checking that all files are of the correct type, and
* just writes the result to stdout, removing headers and padding to
* the right amount. It also writes some system data to stderr.
*/
/*
* Changes by tytso to allow root device specification
* High loaded stuff by Hans Lermen & Werner Almesberger, Feb. 1996
* Cross compiling fixes by Gertjan van Wingerde, July 1996
* Rewritten by Martin Mares, April 1997
*/
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <stdarg.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/sysmacros.h>
#include <unistd.h>
#include <fcntl.h>
#include <asm/boot.h>
#define DEFAULT_MAJOR_ROOT 0
#define DEFAULT_MINOR_ROOT 0
/* Minimal number of setup sectors (see also bootsect.S) */
#define SETUP_SECTS 4
uint8_t buf[1024];
int fd;
int is_big_kernel;
__attribute__((noreturn))
void die(const char *str, ...)
{
va_list args;
va_start(args, str);
vfprintf(stderr, str, args);
fputc('\n', stderr);
exit(1);
}
void file_open(const char *name)
{
fd = open(name, O_RDONLY, 0);
if (fd < 0)
die("Unable to open `%s': %m", name);
}
__attribute__((noreturn))
void usage(void)
{
die("Usage: build [-b] bootsect setup system [rootdev] [> image]");
}
int main(int argc, char **argv)
{
unsigned int i, c, sz, setup_sectors;
uint32_t sys_size;
uint8_t major_root, minor_root;
struct stat sb;
if (argc > 2 && !strcmp(argv[1], "-b")) {
is_big_kernel = 1;
argc--, argv++;
}
if ((argc < 4) || (argc > 5))
usage();
if (argc > 4) {
if (!strcmp(argv[4], "CURRENT")) {
if (stat("/", &sb)) {
perror("/");
die("Couldn't stat /");
}
major_root = major(sb.st_dev);
minor_root = minor(sb.st_dev);
} else if (strcmp(argv[4], "FLOPPY")) {
if (stat(argv[4], &sb)) {
perror(argv[4]);
die("Couldn't stat root device.");
}
major_root = major(sb.st_rdev);
minor_root = minor(sb.st_rdev);
} else {
major_root = 0;
minor_root = 0;
}
} else {
major_root = DEFAULT_MAJOR_ROOT;
minor_root = DEFAULT_MINOR_ROOT;
}
fprintf(stderr, "Root device is (%d, %d)\n", major_root, minor_root);
file_open(argv[1]);
i = read(fd, buf, sizeof(buf));
fprintf(stderr, "Boot sector %d bytes.\n", i);
if (i != 512)
die("Boot block must be exactly 512 bytes");
if (buf[510] != 0x55 || buf[511] != 0xaa)
die("Boot block hasn't got boot flag (0xAA55)");
buf[508] = minor_root;
buf[509] = major_root;
if (write(1, buf, 512) != 512)
die("Write call failed");
close(fd);
/* Copy the setup code */
file_open(argv[2]);
for (i = 0; (c = read(fd, buf, sizeof(buf))) > 0; i += c)
if (write(1, buf, c) != c)
die("Write call failed");
if (c != 0)
die("read-error on `setup'");
close(fd);
/* Pad unused space with zeros */
setup_sectors = (i + 511) / 512;
/* for compatibility with ancient versions of LILO. */
if (setup_sectors < SETUP_SECTS)
setup_sectors = SETUP_SECTS;
fprintf(stderr, "Setup is %d bytes.\n", i);
memset(buf, 0, sizeof(buf));
while (i < setup_sectors * 512) {
c = setup_sectors * 512 - i;
if (c > sizeof(buf))
c = sizeof(buf);
if (write(1, buf, c) != c)
die("Write call failed");
i += c;
}
file_open(argv[3]);
if (fstat(fd, &sb))
die("Unable to stat `%s': %m", argv[3]);
sz = sb.st_size;
fprintf(stderr, "System is %d kB\n", sz / 1024);
sys_size = (sz + 15) / 16;
/* 0x28000*16 = 2.5 MB, conservative estimate for the current maximum */
if (sys_size > (is_big_kernel ? 0x28000 : DEF_SYSSIZE))
die("System is too big. Try using %smodules.",
is_big_kernel ? "" : "bzImage or ");
if (sys_size > 0xffff)
fprintf(stderr,
"warning: kernel is too big for standalone boot "
"from floppy\n");
while (sz > 0) {
int l, n;
l = (sz > sizeof(buf)) ? sizeof(buf) : sz;
n = read(fd, buf, l);
if (n != l) {
if (n < 0)
die("Error reading %s: %m", argv[3]);
else
die("%s: Unexpected EOF", argv[3]);
}
if (write(1, buf, l) != l)
die("Write failed");
sz -= l;
}
close(fd);
/* Write sizes to the bootsector */
if (lseek(1, 497, SEEK_SET) != 497)
die("Output: seek failed");
buf[0] = setup_sectors;
if (write(1, buf, 1) != 1)
die("Write of setup sector count failed");
if (lseek(1, 500, SEEK_SET) != 500)
die("Output: seek failed");
buf[0] = (sys_size & 0xff);
buf[1] = ((sys_size >> 8) & 0xff);
if (write(1, buf, 2) != 2)
die("Write of image length failed");
return 0;
}

67
arch/mn10300/configs/asb2303_defconfig
View file

@ -1,67 +0,0 @@
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_TINY_RCU=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_EXPERT=y
# CONFIG_KALLSYMS is not set
# CONFIG_HOTPLUG is not set
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_SLAB=y
CONFIG_PROFILING=y
# CONFIG_BLOCK is not set
CONFIG_PREEMPT=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_MN10300_RTC=y
CONFIG_MN10300_TTYSM_CONSOLE=y
CONFIG_MN10300_TTYSM0=y
CONFIG_MN10300_TTYSM1=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_MTD=y
CONFIG_MTD_DEBUG=y
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_CFI_I4=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_SMC91X=y
# CONFIG_WLAN is not set
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
# CONFIG_HW_RANDOM is not set
CONFIG_RTC=y
# CONFIG_HWMON is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_PROC_KCORE=y
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_STRIP_ASM_SYMS=y

87
arch/mn10300/configs/asb2364_defconfig
View file

@ -1,87 +0,0 @@
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CGROUPS=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_RELAY=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_EXPERT=y
# CONFIG_KALLSYMS is not set
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_SLAB=y
CONFIG_PROFILING=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLOCK is not set
CONFIG_MN10300_UNIT_ASB2364=y
CONFIG_PREEMPT=y
# CONFIG_MN10300_USING_JTAG is not set
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_MN10300_TTYSM_CONSOLE=y
CONFIG_MN10300_TTYSM0=y
CONFIG_MN10300_TTYSM0_TIMER2=y
CONFIG_MN10300_TTYSM1=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_DIAG is not set
CONFIG_IPV6=y
# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
# CONFIG_INET6_XFRM_MODE_BEET is not set
CONFIG_CONNECTOR=y
CONFIG_MTD=y
CONFIG_MTD_DEBUG=y
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_CFI_I4=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_SMSC911X=y
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_PROC_KCORE=y
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_JFFS2_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_INFO=y

13
arch/mn10300/include/asm/Kbuild
View file

@ -1,13 +0,0 @@
generic-y += barrier.h
generic-y += device.h
generic-y += exec.h
generic-y += extable.h
generic-y += fb.h
generic-y += irq_work.h
generic-y += mcs_spinlock.h
generic-y += mm-arch-hooks.h
generic-y += preempt.h
generic-y += sections.h
generic-y += trace_clock.h
generic-y += word-at-a-time.h

1
arch/mn10300/include/asm/asm-offsets.h
View file

@ -1 +0,0 @@
#include <generated/asm-offsets.h>

161
arch/mn10300/include/asm/atomic.h
View file

@ -1,161 +0,0 @@
/* MN10300 Atomic counter operations
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_ATOMIC_H
#define _ASM_ATOMIC_H
#include <asm/irqflags.h>
#include <asm/cmpxchg.h>
#include <asm/barrier.h>
#ifndef CONFIG_SMP
#include <asm-generic/atomic.h>
#else
/*
* Atomic operations that C can't guarantee us. Useful for
* resource counting etc..
*/
#define ATOMIC_INIT(i) { (i) }
#ifdef __KERNEL__
/**
* atomic_read - read atomic variable
* @v: pointer of type atomic_t
*
* Atomically reads the value of @v. Note that the guaranteed
*/
#define atomic_read(v) READ_ONCE((v)->counter)
/**
* atomic_set - set atomic variable
* @v: pointer of type atomic_t
* @i: required value
*
* Atomically sets the value of @v to @i. Note that the guaranteed
*/
#define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
#define ATOMIC_OP(op) \
static inline void atomic_##op(int i, atomic_t *v) \
{ \
int retval, status; \
\
asm volatile( \
"1: mov %4,(_AAR,%3) \n" \
" mov (_ADR,%3),%1 \n" \
" " #op " %5,%1 \n" \
" mov %1,(_ADR,%3) \n" \
" mov (_ADR,%3),%0 \n" /* flush */ \
" mov (_ASR,%3),%0 \n" \
" or %0,%0 \n" \
" bne 1b \n" \
: "=&r"(status), "=&r"(retval), "=m"(v->counter) \
: "a"(ATOMIC_OPS_BASE_ADDR), "r"(&v->counter), "r"(i) \
: "memory", "cc"); \
}
#define ATOMIC_OP_RETURN(op) \
static inline int atomic_##op##_return(int i, atomic_t *v) \
{ \
int retval, status; \
\
asm volatile( \
"1: mov %4,(_AAR,%3) \n" \
" mov (_ADR,%3),%1 \n" \
" " #op " %5,%1 \n" \
" mov %1,(_ADR,%3) \n" \
" mov (_ADR,%3),%0 \n" /* flush */ \
" mov (_ASR,%3),%0 \n" \
" or %0,%0 \n" \
" bne 1b \n" \
: "=&r"(status), "=&r"(retval), "=m"(v->counter) \
: "a"(ATOMIC_OPS_BASE_ADDR), "r"(&v->counter), "r"(i) \
: "memory", "cc"); \
return retval; \
}
#define ATOMIC_FETCH_OP(op) \
static inline int atomic_fetch_##op(int i, atomic_t *v) \
{ \
int retval, status; \
\
asm volatile( \
"1: mov %4,(_AAR,%3) \n" \
" mov (_ADR,%3),%1 \n" \
" mov %1,%0 \n" \
" " #op " %5,%0 \n" \
" mov %0,(_ADR,%3) \n" \
" mov (_ADR,%3),%0 \n" /* flush */ \
" mov (_ASR,%3),%0 \n" \
" or %0,%0 \n" \
" bne 1b \n" \
: "=&r"(status), "=&r"(retval), "=m"(v->counter) \
: "a"(ATOMIC_OPS_BASE_ADDR), "r"(&v->counter), "r"(i) \
: "memory", "cc"); \
return retval; \
}
#define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_OP_RETURN(op) ATOMIC_FETCH_OP(op)
ATOMIC_OPS(add)
ATOMIC_OPS(sub)
#undef ATOMIC_OPS
#define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op)
ATOMIC_OPS(and)
ATOMIC_OPS(or)
ATOMIC_OPS(xor)
#undef ATOMIC_OPS
#undef ATOMIC_FETCH_OP
#undef ATOMIC_OP_RETURN
#undef ATOMIC_OP
static inline int atomic_add_negative(int i, atomic_t *v)
{
return atomic_add_return(i, v) < 0;
}
static inline void atomic_inc(atomic_t *v)
{
atomic_add_return(1, v);
}
static inline void atomic_dec(atomic_t *v)
{
atomic_sub_return(1, v);
}
#define atomic_dec_return(v) atomic_sub_return(1, (v))
#define atomic_inc_return(v) atomic_add_return(1, (v))
#define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0)
#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
#define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0)
#define __atomic_add_unless(v, a, u) \
({ \
int c, old; \
c = atomic_read(v); \
while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
c = old; \
c; \
})
#define atomic_xchg(ptr, v) (xchg(&(ptr)->counter, (v)))
#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), (old), (new)))
#endif /* __KERNEL__ */
#endif /* CONFIG_SMP */
#endif /* _ASM_ATOMIC_H */

232
arch/mn10300/include/asm/bitops.h
View file

@ -1,232 +0,0 @@
/* MN10300 bit operations
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*
* These have to be done with inline assembly: that way the bit-setting
* is guaranteed to be atomic. All bit operations return 0 if the bit
* was cleared before the operation and != 0 if it was not.
*
* bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
*/
#ifndef __ASM_BITOPS_H
#define __ASM_BITOPS_H
#include <asm/cpu-regs.h>
#include <asm/barrier.h>
/*
* set bit
*/
#define __set_bit(nr, addr) \
({ \
volatile unsigned char *_a = (unsigned char *)(addr); \
const unsigned shift = (nr) & 7; \
_a += (nr) >> 3; \
\
asm volatile("bset %2,(%1) # set_bit reg" \
: "=m"(*_a) \
: "a"(_a), "d"(1 << shift), "m"(*_a) \
: "memory", "cc"); \
})
#define set_bit(nr, addr) __set_bit((nr), (addr))
/*
* clear bit
*/
#define ___clear_bit(nr, addr) \
({ \
volatile unsigned char *_a = (unsigned char *)(addr); \
const unsigned shift = (nr) & 7; \
_a += (nr) >> 3; \
\
asm volatile("bclr %2,(%1) # clear_bit reg" \
: "=m"(*_a) \
: "a"(_a), "d"(1 << shift), "m"(*_a) \
: "memory", "cc"); \
})
#define clear_bit(nr, addr) ___clear_bit((nr), (addr))
static inline void __clear_bit(unsigned long nr, volatile void *addr)
{
unsigned int *a = (unsigned int *) addr;
int mask;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
*a &= ~mask;
}
/*
* test bit
*/
static inline int test_bit(unsigned long nr, const volatile void *addr)
{
return 1UL & (((const volatile unsigned int *) addr)[nr >> 5] >> (nr & 31));
}
/*
* change bit
*/
static inline void __change_bit(unsigned long nr, volatile void *addr)
{
int mask;
unsigned int *a = (unsigned int *) addr;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
*a ^= mask;
}
extern void change_bit(unsigned long nr, volatile void *addr);
/*
* test and set bit
*/
#define __test_and_set_bit(nr,addr) \
({ \
volatile unsigned char *_a = (unsigned char *)(addr); \
const unsigned shift = (nr) & 7; \
unsigned epsw; \
_a += (nr) >> 3; \
\
asm volatile("bset %3,(%2) # test_set_bit reg\n" \
"mov epsw,%1" \
: "=m"(*_a), "=d"(epsw) \
: "a"(_a), "d"(1 << shift), "m"(*_a) \
: "memory", "cc"); \
\
!(epsw & EPSW_FLAG_Z); \
})
#define test_and_set_bit(nr, addr) __test_and_set_bit((nr), (addr))
/*
* test and clear bit
*/
#define __test_and_clear_bit(nr, addr) \
({ \
volatile unsigned char *_a = (unsigned char *)(addr); \
const unsigned shift = (nr) & 7; \
unsigned epsw; \
_a += (nr) >> 3; \
\
asm volatile("bclr %3,(%2) # test_clear_bit reg\n" \
"mov epsw,%1" \
: "=m"(*_a), "=d"(epsw) \
: "a"(_a), "d"(1 << shift), "m"(*_a) \
: "memory", "cc"); \
\
!(epsw & EPSW_FLAG_Z); \
})
#define test_and_clear_bit(nr, addr) __test_and_clear_bit((nr), (addr))
/*
* test and change bit
*/
static inline int __test_and_change_bit(unsigned long nr, volatile void *addr)
{
int mask, retval;
unsigned int *a = (unsigned int *)addr;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
retval = (mask & *a) != 0;
*a ^= mask;
return retval;
}
extern int test_and_change_bit(unsigned long nr, volatile void *addr);
#include <asm-generic/bitops/lock.h>
#ifdef __KERNEL__
/**
* __ffs - find first bit set
* @x: the word to search
*
* - return 31..0 to indicate bit 31..0 most least significant bit set
* - if no bits are set in x, the result is undefined
*/
static inline __attribute__((const))
unsigned long __ffs(unsigned long x)
{
int bit;
asm("bsch %2,%0" : "=r"(bit) : "0"(0), "r"(x & -x) : "cc");
return bit;
}
/*
* special slimline version of fls() for calculating ilog2_u32()
* - note: no protection against n == 0
*/
static inline __attribute__((const))
int __ilog2_u32(u32 n)
{
int bit;
asm("bsch %2,%0" : "=r"(bit) : "0"(0), "r"(n) : "cc");
return bit;
}
/**
* fls - find last bit set
* @x: the word to search
*
* This is defined the same way as ffs:
* - return 32..1 to indicate bit 31..0 most significant bit set
* - return 0 to indicate no bits set
*/
static inline __attribute__((const))
int fls(int x)
{
return (x != 0) ? __ilog2_u32(x) + 1 : 0;
}
/**
* __fls - find last (most-significant) set bit in a long word
* @word: the word to search
*
* Undefined if no set bit exists, so code should check against 0 first.
*/
static inline unsigned long __fls(unsigned long word)
{
return __ilog2_u32(word);
}
/**
* ffs - find first bit set
* @x: the word to search
*
* - return 32..1 to indicate bit 31..0 most least significant bit set
* - return 0 to indicate no bits set
*/
static inline __attribute__((const))
int ffs(int x)
{
/* Note: (x & -x) gives us a mask that is the least significant
* (rightmost) 1-bit of the value in x.
*/
return fls(x & -x);
}
#include <asm-generic/bitops/ffz.h>
#include <asm-generic/bitops/fls64.h>
#include <asm-generic/bitops/find.h>
#include <asm-generic/bitops/sched.h>
#include <asm-generic/bitops/hweight.h>
#include <asm-generic/bitops/ext2-atomic-setbit.h>
#include <asm-generic/bitops/le.h>
#endif /* __KERNEL__ */
#endif /* __ASM_BITOPS_H */

37
arch/mn10300/include/asm/bug.h
View file

@ -1,37 +0,0 @@
/* MN10300 Kernel bug reporting
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_BUG_H
#define _ASM_BUG_H
#ifdef CONFIG_BUG
/*
* Tell the user there is some problem.
*/
#define BUG() \
do { \
asm volatile( \
" syscall 15 \n" \
"0: \n" \
" .section __bug_table,\"aw\" \n" \
" .long 0b,%0,%1 \n" \
" .previous \n" \
: \
: "i"(__FILE__), "i"(__LINE__) \
); \
} while (1)
#define HAVE_ARCH_BUG
#endif /* CONFIG_BUG */
#include <asm-generic/bug.h>
#endif /* _ASM_BUG_H */

20
arch/mn10300/include/asm/bugs.h
View file

@ -1,20 +0,0 @@
/* MN10300 Checks for architecture-dependent bugs
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_BUGS_H
#define _ASM_BUGS_H
#include <asm/processor.h>
static inline void __init check_bugs(void)
{
}
#endif /* _ASM_BUGS_H */

151
arch/mn10300/include/asm/busctl-regs.h
View file

@ -1,151 +0,0 @@
/* AM33v2 on-board bus controller registers
*
* Copyright (C) 2002 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_BUSCTL_REGS_H
#define _ASM_BUSCTL_REGS_H
#include <asm/cpu-regs.h>
#ifdef __KERNEL__
/* bus controller registers */
#define BCCR __SYSREG(0xc0002000, u32) /* bus controller control reg */
#define BCCR_B0AD 0x00000003 /* block 0 (80000000-83ffffff) bus allocation */
#define BCCR_B1AD 0x0000000c /* block 1 (84000000-87ffffff) bus allocation */
#define BCCR_B2AD 0x00000030 /* block 2 (88000000-8bffffff) bus allocation */
#define BCCR_B3AD 0x000000c0 /* block 3 (8c000000-8fffffff) bus allocation */
#define BCCR_B4AD 0x00000300 /* block 4 (90000000-93ffffff) bus allocation */
#define BCCR_B5AD 0x00000c00 /* block 5 (94000000-97ffffff) bus allocation */
#define BCCR_B6AD 0x00003000 /* block 6 (98000000-9bffffff) bus allocation */
#define BCCR_B7AD 0x0000c000 /* block 7 (9c000000-9fffffff) bus allocation */
#define BCCR_BxAD_EXBUS 0x0 /* - direct to system bus controller */
#define BCCR_BxAD_OPEXBUS 0x1 /* - direct to memory bus controller */
#define BCCR_BxAD_OCMBUS 0x2 /* - direct to on chip memory */
#define BCCR_API 0x00070000 /* bus arbitration priority */
#define BCCR_API_DMACICD 0x00000000 /* - DMA > CI > CD */
#define BCCR_API_DMACDCI 0x00010000 /* - DMA > CD > CI */
#define BCCR_API_CICDDMA 0x00020000 /* - CI > CD > DMA */
#define BCCR_API_CDCIDMA 0x00030000 /* - CD > CI > DMA */
#define BCCR_API_ROUNDROBIN 0x00040000 /* - round robin */
#define BCCR_BEPRI_DMACICD 0x00c00000 /* bus error address priority */
#define BCCR_BEPRI_DMACDCI 0x00000000 /* - DMA > CI > CD */
#define BCCR_BEPRI_CICDDMA 0x00400000 /* - DMA > CD > CI */
#define BCCR_BEPRI_CDCIDMA 0x00800000 /* - CI > CD > DMA */
#define BCCR_BEPRI 0x00c00000 /* - CD > CI > DMA */
#define BCCR_TMON 0x03000000 /* timeout value settings */
#define BCCR_TMON_16IOCLK 0x00000000 /* - 16 IOCLK cycles */
#define BCCR_TMON_256IOCLK 0x01000000 /* - 256 IOCLK cycles */
#define BCCR_TMON_4096IOCLK 0x02000000 /* - 4096 IOCLK cycles */
#define BCCR_TMON_65536IOCLK 0x03000000 /* - 65536 IOCLK cycles */
#define BCCR_TMOE 0x10000000 /* timeout detection enable */
#define BCBERR __SYSREG(0xc0002010, u32) /* bus error source reg */
#define BCBERR_BESB 0x0000001f /* erroneous access destination space */
#define BCBERR_BESB_MON 0x00000001 /* - monitor space */
#define BCBERR_BESB_IO 0x00000002 /* - IO bus */
#define BCBERR_BESB_EX 0x00000004 /* - EX bus */
#define BCBERR_BESB_OPEX 0x00000008 /* - OpEX bus */
#define BCBERR_BESB_OCM 0x00000010 /* - on chip memory */
#define BCBERR_BERW 0x00000100 /* type of access */
#define BCBERR_BERW_WRITE 0x00000000 /* - write */
#define BCBERR_BERW_READ 0x00000100 /* - read */
#define BCBERR_BESD 0x00000200 /* error detector */
#define BCBERR_BESD_BCU 0x00000000 /* - BCU detected error */
#define BCBERR_BESD_SLAVE_BUS 0x00000200 /* - slave bus detected error */
#define BCBERR_BEBST 0x00000400 /* type of access */
#define BCBERR_BEBST_SINGLE 0x00000000 /* - single */
#define BCBERR_BEBST_BURST 0x00000400 /* - burst */
#define BCBERR_BEME 0x00000800 /* multiple bus error flag */
#define BCBERR_BEMR 0x00007000 /* master bus that caused the error */
#define BCBERR_BEMR_NOERROR 0x00000000 /* - no error */
#define BCBERR_BEMR_CI 0x00001000 /* - CPU instruction fetch bus caused error */
#define BCBERR_BEMR_CD 0x00002000 /* - CPU data bus caused error */
#define BCBERR_BEMR_DMA 0x00004000 /* - DMA bus caused error */
#define BCBEAR __SYSREGC(0xc0002020, u32) /* bus error address reg */
/* system bus controller registers */
#define SBBASE(X) __SYSREG(0xd8c00100 + (X) * 0x10, u32) /* SBC base addr regs */
#define SBBASE_BE 0x00000001 /* bank enable */
#define SBBASE_BAM 0x0000fffe /* bank address mask [31:17] */
#define SBBASE_BBA 0xfffe0000 /* bank base address [31:17] */
#define SBCNTRL0(X) __SYSREG(0xd8c00200 + (X) * 0x10, u32) /* SBC bank ctrl0 regs */
#define SBCNTRL0_WEH 0x00000f00 /* write enable hold */
#define SBCNTRL0_REH 0x0000f000 /* read enable hold */
#define SBCNTRL0_RWH 0x000f0000 /* SRW signal hold */
#define SBCNTRL0_CSH 0x00f00000 /* chip select hold */
#define SBCNTRL0_DAH 0x0f000000 /* data hold */
#define SBCNTRL0_ADH 0xf0000000 /* address hold */
#define SBCNTRL1(X) __SYSREG(0xd8c00204 + (X) * 0x10, u32) /* SBC bank ctrl1 regs */
#define SBCNTRL1_WED 0x00000f00 /* write enable delay */
#define SBCNTRL1_RED 0x0000f000 /* read enable delay */
#define SBCNTRL1_RWD 0x000f0000 /* SRW signal delay */
#define SBCNTRL1_ASW 0x00f00000 /* address strobe width */
#define SBCNTRL1_CSD 0x0f000000 /* chip select delay */
#define SBCNTRL1_ASD 0xf0000000 /* address strobe delay */
#define SBCNTRL2(X) __SYSREG(0xd8c00208 + (X) * 0x10, u32) /* SBC bank ctrl2 regs */
#define SBCNTRL2_WC 0x000000ff /* wait count */
#define SBCNTRL2_BWC 0x00000f00 /* burst wait count */
#define SBCNTRL2_WM 0x01000000 /* wait mode setting */
#define SBCNTRL2_WM_FIXEDWAIT 0x00000000 /* - fixed wait access */
#define SBCNTRL2_WM_HANDSHAKE 0x01000000 /* - handshake access */
#define SBCNTRL2_BM 0x02000000 /* bus synchronisation mode */
#define SBCNTRL2_BM_SYNC 0x00000000 /* - synchronous mode */
#define SBCNTRL2_BM_ASYNC 0x02000000 /* - asynchronous mode */
#define SBCNTRL2_BW 0x04000000 /* bus width */
#define SBCNTRL2_BW_32 0x00000000 /* - 32 bits */
#define SBCNTRL2_BW_16 0x04000000 /* - 16 bits */
#define SBCNTRL2_RWINV 0x08000000 /* R/W signal invert polarity */
#define SBCNTRL2_RWINV_NORM 0x00000000 /* - normal (read high) */
#define SBCNTRL2_RWINV_INV 0x08000000 /* - inverted (read low) */
#define SBCNTRL2_BT 0x70000000 /* bus type setting */
#define SBCNTRL2_BT_SRAM 0x00000000 /* - SRAM interface */
#define SBCNTRL2_BT_ADMUX 0x00000000 /* - addr/data multiplexed interface */
#define SBCNTRL2_BT_BROM 0x00000000 /* - burst ROM interface */
#define SBCNTRL2_BTSE 0x80000000 /* burst enable */
/* memory bus controller */
#define SDBASE(X) __SYSREG(0xda000008 + (X) * 0x4, u32) /* MBC base addr regs */
#define SDBASE_CE 0x00000001 /* chip enable */
#define SDBASE_CBAM 0x0000fff0 /* chip base address mask [31:20] */
#define SDBASE_CBAM_SHIFT 16
#define SDBASE_CBA 0xfff00000 /* chip base address [31:20] */
#define SDRAMBUS __SYSREG(0xda000000, u32) /* bus mode control reg */
#define SDRAMBUS_REFEN 0x00000004 /* refresh enable */
#define SDRAMBUS_TRC 0x00000018 /* refresh command delay time */
#define SDRAMBUS_BSTPT 0x00000020 /* burst stop command enable */
#define SDRAMBUS_PONSEQ 0x00000040 /* power on sequence */
#define SDRAMBUS_SELFREQ 0x00000080 /* self-refresh mode request */
#define SDRAMBUS_SELFON 0x00000100 /* self-refresh mode on */
#define SDRAMBUS_SIZE 0x00030000 /* SDRAM size */
#define SDRAMBUS_SIZE_64Mbit 0x00010000 /* 64Mbit SDRAM (x16) */
#define SDRAMBUS_SIZE_128Mbit 0x00020000 /* 128Mbit SDRAM (x16) */
#define SDRAMBUS_SIZE_256Mbit 0x00030000 /* 256Mbit SDRAM (x16) */
#define SDRAMBUS_TRASWAIT 0x000c0000 /* row address precharge command cycle number */
#define SDRAMBUS_REFNUM 0x00300000 /* refresh command number */
#define SDRAMBUS_BSTWAIT 0x00c00000 /* burst stop command cycle */
#define SDRAMBUS_SETWAIT 0x03000000 /* mode register setting command cycle */
#define SDRAMBUS_PREWAIT 0x0c000000 /* precharge command cycle */
#define SDRAMBUS_RASLATE 0x30000000 /* RAS latency */
#define SDRAMBUS_CASLATE 0xc0000000 /* CAS latency */
#define SDREFCNT __SYSREG(0xda000004, u32) /* refresh period reg */
#define SDREFCNT_PERI 0x00000fff /* refresh period */
#define SDSHDW __SYSREG(0xda000010, u32) /* test reg */
#endif /* __KERNEL__ */
#endif /* _ASM_BUSCTL_REGS_H */

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arch/mn10300/include/asm/cache.h
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/* MN10300 cache management registers
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_CACHE_H
#define _ASM_CACHE_H
#include <asm/cpu-regs.h>
#include <proc/cache.h>
#ifndef __ASSEMBLY__
#define L1_CACHE_DISPARITY (L1_CACHE_NENTRIES * L1_CACHE_BYTES)
#else
#define L1_CACHE_DISPARITY L1_CACHE_NENTRIES * L1_CACHE_BYTES
#endif
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
/* data cache purge registers
* - read from the register to unconditionally purge that cache line
* - write address & 0xffffff00 to conditionally purge that cache line
* - clear LSB to request invalidation as well
*/
#define DCACHE_PURGE(WAY, ENTRY) \
__SYSREG(0xc8400000 + (WAY) * L1_CACHE_WAYDISP + \
(ENTRY) * L1_CACHE_BYTES, u32)
#define DCACHE_PURGE_WAY0(ENTRY) \
__SYSREG(0xc8400000 + 0 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
#define DCACHE_PURGE_WAY1(ENTRY) \
__SYSREG(0xc8400000 + 1 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
#define DCACHE_PURGE_WAY2(ENTRY) \
__SYSREG(0xc8400000 + 2 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
#define DCACHE_PURGE_WAY3(ENTRY) \
__SYSREG(0xc8400000 + 3 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
/* instruction cache access registers */
#define ICACHE_DATA(WAY, ENTRY, OFF) \
__SYSREG(0xc8000000 + (WAY) * L1_CACHE_WAYDISP + \
(ENTRY) * L1_CACHE_BYTES + (OFF) * 4, u32)
#define ICACHE_TAG(WAY, ENTRY) \
__SYSREG(0xc8100000 + (WAY) * L1_CACHE_WAYDISP + \
(ENTRY) * L1_CACHE_BYTES, u32)
/* data cache access registers */
#define DCACHE_DATA(WAY, ENTRY, OFF) \
__SYSREG(0xc8200000 + (WAY) * L1_CACHE_WAYDISP + \
(ENTRY) * L1_CACHE_BYTES + (OFF) * 4, u32)
#define DCACHE_TAG(WAY, ENTRY) \
__SYSREG(0xc8300000 + (WAY) * L1_CACHE_WAYDISP + \
(ENTRY) * L1_CACHE_BYTES, u32)
#endif /* _ASM_CACHE_H */

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arch/mn10300/include/asm/cacheflush.h
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/* MN10300 Cache flushing
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_CACHEFLUSH_H
#define _ASM_CACHEFLUSH_H
#ifndef __ASSEMBLY__
/* Keep includes the same across arches. */
#include <linux/mm.h>
/*
* Primitive routines
*/
#ifdef CONFIG_MN10300_CACHE_ENABLED
extern void mn10300_local_icache_inv(void);
extern void mn10300_local_icache_inv_page(unsigned long start);
extern void mn10300_local_icache_inv_range(unsigned long start, unsigned long end);
extern void mn10300_local_icache_inv_range2(unsigned long start, unsigned long size);
extern void mn10300_local_dcache_inv(void);
extern void mn10300_local_dcache_inv_page(unsigned long start);
extern void mn10300_local_dcache_inv_range(unsigned long start, unsigned long end);
extern void mn10300_local_dcache_inv_range2(unsigned long start, unsigned long size);
extern void mn10300_icache_inv(void);
extern void mn10300_icache_inv_page(unsigned long start);
extern void mn10300_icache_inv_range(unsigned long start, unsigned long end);
extern void mn10300_icache_inv_range2(unsigned long start, unsigned long size);
extern void mn10300_dcache_inv(void);
extern void mn10300_dcache_inv_page(unsigned long start);
extern void mn10300_dcache_inv_range(unsigned long start, unsigned long end);
extern void mn10300_dcache_inv_range2(unsigned long start, unsigned long size);
#ifdef CONFIG_MN10300_CACHE_WBACK
extern void mn10300_local_dcache_flush(void);
extern void mn10300_local_dcache_flush_page(unsigned long start);
extern void mn10300_local_dcache_flush_range(unsigned long start, unsigned long end);
extern void mn10300_local_dcache_flush_range2(unsigned long start, unsigned long size);
extern void mn10300_local_dcache_flush_inv(void);
extern void mn10300_local_dcache_flush_inv_page(unsigned long start);
extern void mn10300_local_dcache_flush_inv_range(unsigned long start, unsigned long end);
extern void mn10300_local_dcache_flush_inv_range2(unsigned long start, unsigned long size);
extern void mn10300_dcache_flush(void);
extern void mn10300_dcache_flush_page(unsigned long start);
extern void mn10300_dcache_flush_range(unsigned long start, unsigned long end);
extern void mn10300_dcache_flush_range2(unsigned long start, unsigned long size);
extern void mn10300_dcache_flush_inv(void);
extern void mn10300_dcache_flush_inv_page(unsigned long start);
extern void mn10300_dcache_flush_inv_range(unsigned long start, unsigned long end);
extern void mn10300_dcache_flush_inv_range2(unsigned long start, unsigned long size);
#else
#define mn10300_local_dcache_flush() do {} while (0)
#define mn10300_local_dcache_flush_page(start) do {} while (0)
#define mn10300_local_dcache_flush_range(start, end) do {} while (0)
#define mn10300_local_dcache_flush_range2(start, size) do {} while (0)
#define mn10300_local_dcache_flush_inv() \
mn10300_local_dcache_inv()
#define mn10300_local_dcache_flush_inv_page(start) \
mn10300_local_dcache_inv_page(start)
#define mn10300_local_dcache_flush_inv_range(start, end) \
mn10300_local_dcache_inv_range(start, end)
#define mn10300_local_dcache_flush_inv_range2(start, size) \
mn10300_local_dcache_inv_range2(start, size)
#define mn10300_dcache_flush() do {} while (0)
#define mn10300_dcache_flush_page(start) do {} while (0)
#define mn10300_dcache_flush_range(start, end) do {} while (0)
#define mn10300_dcache_flush_range2(start, size) do {} while (0)
#define mn10300_dcache_flush_inv() mn10300_dcache_inv()
#define mn10300_dcache_flush_inv_page(start) \
mn10300_dcache_inv_page((start))
#define mn10300_dcache_flush_inv_range(start, end) \
mn10300_dcache_inv_range((start), (end))
#define mn10300_dcache_flush_inv_range2(start, size) \
mn10300_dcache_inv_range2((start), (size))
#endif /* CONFIG_MN10300_CACHE_WBACK */
#else
#define mn10300_local_icache_inv() do {} while (0)
#define mn10300_local_icache_inv_page(start) do {} while (0)
#define mn10300_local_icache_inv_range(start, end) do {} while (0)
#define mn10300_local_icache_inv_range2(start, size) do {} while (0)
#define mn10300_local_dcache_inv() do {} while (0)
#define mn10300_local_dcache_inv_page(start) do {} while (0)
#define mn10300_local_dcache_inv_range(start, end) do {} while (0)
#define mn10300_local_dcache_inv_range2(start, size) do {} while (0)
#define mn10300_local_dcache_flush() do {} while (0)
#define mn10300_local_dcache_flush_inv_page(start) do {} while (0)
#define mn10300_local_dcache_flush_inv() do {} while (0)
#define mn10300_local_dcache_flush_inv_range(start, end)do {} while (0)
#define mn10300_local_dcache_flush_inv_range2(start, size) do {} while (0)
#define mn10300_local_dcache_flush_page(start) do {} while (0)
#define mn10300_local_dcache_flush_range(start, end) do {} while (0)
#define mn10300_local_dcache_flush_range2(start, size) do {} while (0)
#define mn10300_icache_inv() do {} while (0)
#define mn10300_icache_inv_page(start) do {} while (0)
#define mn10300_icache_inv_range(start, end) do {} while (0)
#define mn10300_icache_inv_range2(start, size) do {} while (0)
#define mn10300_dcache_inv() do {} while (0)
#define mn10300_dcache_inv_page(start) do {} while (0)
#define mn10300_dcache_inv_range(start, end) do {} while (0)
#define mn10300_dcache_inv_range2(start, size) do {} while (0)
#define mn10300_dcache_flush() do {} while (0)
#define mn10300_dcache_flush_inv_page(start) do {} while (0)
#define mn10300_dcache_flush_inv() do {} while (0)
#define mn10300_dcache_flush_inv_range(start, end) do {} while (0)
#define mn10300_dcache_flush_inv_range2(start, size) do {} while (0)
#define mn10300_dcache_flush_page(start) do {} while (0)
#define mn10300_dcache_flush_range(start, end) do {} while (0)
#define mn10300_dcache_flush_range2(start, size) do {} while (0)
#endif /* CONFIG_MN10300_CACHE_ENABLED */
/*
* Virtually-indexed cache management (our cache is physically indexed)
*/
#define flush_cache_all() do {} while (0)
#define flush_cache_mm(mm) do {} while (0)
#define flush_cache_dup_mm(mm) do {} while (0)
#define flush_cache_range(mm, start, end) do {} while (0)
#define flush_cache_page(vma, vmaddr, pfn) do {} while (0)
#define flush_cache_vmap(start, end) do {} while (0)
#define flush_cache_vunmap(start, end) do {} while (0)
#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
#define flush_dcache_page(page) do {} while (0)
#define flush_dcache_mmap_lock(mapping) do {} while (0)
#define flush_dcache_mmap_unlock(mapping) do {} while (0)
/*
* Physically-indexed cache management
*/
#if defined(CONFIG_MN10300_CACHE_FLUSH_ICACHE)
extern void flush_icache_page(struct vm_area_struct *vma, struct page *page);
extern void flush_icache_range(unsigned long start, unsigned long end);
#elif defined(CONFIG_MN10300_CACHE_INV_ICACHE)
static inline void flush_icache_page(struct vm_area_struct *vma,
struct page *page)
{
mn10300_icache_inv_page(page_to_phys(page));
}
extern void flush_icache_range(unsigned long start, unsigned long end);
#else
#define flush_icache_range(start, end) do {} while (0)
#define flush_icache_page(vma, pg) do {} while (0)
#endif
#define flush_icache_user_range(vma, pg, adr, len) \
flush_icache_range(adr, adr + len)
#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
do { \
memcpy(dst, src, len); \
flush_icache_page(vma, page); \
} while (0)
#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
memcpy(dst, src, len)
#endif /* __ASSEMBLY__ */
#endif /* _ASM_CACHEFLUSH_H */

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arch/mn10300/include/asm/checksum.h
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/* MN10300 Optimised checksumming code
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_CHECKSUM_H
#define _ASM_CHECKSUM_H
extern __wsum csum_partial(const void *buff, int len, __wsum sum);
extern __wsum csum_partial_copy_nocheck(const void *src, void *dst,
int len, __wsum sum);
extern __wsum csum_partial_copy_from_user(const void *src, void *dst,
int len, __wsum sum,
int *err_ptr);
extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
extern __wsum csum_partial(const void *buff, int len, __wsum sum);
extern __sum16 ip_compute_csum(const void *buff, int len);
#define csum_partial_copy_fromuser csum_partial_copy
extern __wsum csum_partial_copy(const void *src, void *dst, int len,
__wsum sum);
static inline __sum16 csum_fold(__wsum sum)
{
asm(
" add %1,%0 \n"
" addc 0xffff,%0 \n"
: "=r" (sum)
: "r" (sum << 16), "0" (sum & 0xffff0000)
: "cc"
);
return (~sum) >> 16;
}
static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
__u32 len, __u8 proto,
__wsum sum)
{
__wsum tmp = (__wsum)((len + proto) << 8);
asm(
" add %1,%0 \n"
" addc %2,%0 \n"
" addc %3,%0 \n"
" addc 0,%0 \n"
: "=r" (sum)
: "r" (daddr), "r"(saddr), "r"(tmp), "0"(sum)
: "cc"
);
return sum;
}
/*
* computes the checksum of the TCP/UDP pseudo-header
* returns a 16-bit checksum, already complemented
*/
static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
__u32 len, __u8 proto,
__wsum sum)
{
return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
}
#undef _HAVE_ARCH_IPV6_CSUM
/*
* Copy and checksum to user
*/
#define HAVE_CSUM_COPY_USER
extern __wsum csum_and_copy_to_user(const void *src, void *dst, int len,
__wsum sum, int *err_ptr);
#endif /* _ASM_CHECKSUM_H */

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arch/mn10300/include/asm/cmpxchg.h
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/* MN10300 Atomic xchg/cmpxchg operations
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_CMPXCHG_H
#define _ASM_CMPXCHG_H
#include <asm/irqflags.h>
#ifdef CONFIG_SMP
#ifdef CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
static inline
unsigned long __xchg(volatile unsigned long *m, unsigned long val)
{
unsigned long status;
unsigned long oldval;
asm volatile(
"1: mov %4,(_AAR,%3) \n"
" mov (_ADR,%3),%1 \n"
" mov %5,(_ADR,%3) \n"
" mov (_ADR,%3),%0 \n" /* flush */
" mov (_ASR,%3),%0 \n"
" or %0,%0 \n"
" bne 1b \n"
: "=&r"(status), "=&r"(oldval), "=m"(*m)
: "a"(ATOMIC_OPS_BASE_ADDR), "r"(m), "r"(val)
: "memory", "cc");
return oldval;
}
static inline unsigned long __cmpxchg(volatile unsigned long *m,
unsigned long old, unsigned long new)
{
unsigned long status;
unsigned long oldval;
asm volatile(
"1: mov %4,(_AAR,%3) \n"
" mov (_ADR,%3),%1 \n"
" cmp %5,%1 \n"
" bne 2f \n"
" mov %6,(_ADR,%3) \n"
"2: mov (_ADR,%3),%0 \n" /* flush */
" mov (_ASR,%3),%0 \n"
" or %0,%0 \n"
" bne 1b \n"
: "=&r"(status), "=&r"(oldval), "=m"(*m)
: "a"(ATOMIC_OPS_BASE_ADDR), "r"(m),
"r"(old), "r"(new)
: "memory", "cc");
return oldval;
}
#else /* CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT */
#error "No SMP atomic operation support!"
#endif /* CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT */
#else /* CONFIG_SMP */
/*
* Emulate xchg for non-SMP MN10300
*/
struct __xchg_dummy { unsigned long a[100]; };
#define __xg(x) ((struct __xchg_dummy *)(x))
static inline
unsigned long __xchg(volatile unsigned long *m, unsigned long val)
{
unsigned long oldval;
unsigned long flags;
flags = arch_local_cli_save();
oldval = *m;
*m = val;
arch_local_irq_restore(flags);
return oldval;
}
/*
* Emulate cmpxchg for non-SMP MN10300
*/
static inline unsigned long __cmpxchg(volatile unsigned long *m,
unsigned long old, unsigned long new)
{
unsigned long oldval;
unsigned long flags;
flags = arch_local_cli_save();
oldval = *m;
if (oldval == old)
*m = new;
arch_local_irq_restore(flags);
return oldval;
}
#endif /* CONFIG_SMP */
#define xchg(ptr, v) \
((__typeof__(*(ptr))) __xchg((unsigned long *)(ptr), \
(unsigned long)(v)))
#define cmpxchg(ptr, o, n) \
((__typeof__(*(ptr))) __cmpxchg((unsigned long *)(ptr), \
(unsigned long)(o), \
(unsigned long)(n)))
#endif /* _ASM_CMPXCHG_H */

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arch/mn10300/include/asm/cpu-regs.h
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/* MN10300 Core system registers
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_CPU_REGS_H
#define _ASM_CPU_REGS_H
#ifndef __ASSEMBLY__
#include <linux/types.h>
#endif
/* we tell the compiler to pretend to be AM33 so that it doesn't try and use
* the FP regs, but tell the assembler that we're actually allowed AM33v2
* instructions */
#ifndef __ASSEMBLY__
asm(" .am33_2\n");
#else
.am33_2
#endif
#ifdef __KERNEL__
#ifndef __ASSEMBLY__
#define __SYSREG(ADDR, TYPE) (*(volatile TYPE *)(ADDR))
#define __SYSREGC(ADDR, TYPE) (*(const volatile TYPE *)(ADDR))
#else
#define __SYSREG(ADDR, TYPE) ADDR
#define __SYSREGC(ADDR, TYPE) ADDR
#endif
/* CPU registers */
#define EPSW_FLAG_Z 0x00000001 /* zero flag */
#define EPSW_FLAG_N 0x00000002 /* negative flag */
#define EPSW_FLAG_C 0x00000004 /* carry flag */
#define EPSW_FLAG_V 0x00000008 /* overflow flag */
#define EPSW_IM 0x00000700 /* interrupt mode */
#define EPSW_IM_0 0x00000000 /* interrupt mode 0 */
#define EPSW_IM_1 0x00000100 /* interrupt mode 1 */
#define EPSW_IM_2 0x00000200 /* interrupt mode 2 */
#define EPSW_IM_3 0x00000300 /* interrupt mode 3 */
#define EPSW_IM_4 0x00000400 /* interrupt mode 4 */
#define EPSW_IM_5 0x00000500 /* interrupt mode 5 */
#define EPSW_IM_6 0x00000600 /* interrupt mode 6 */
#define EPSW_IM_7 0x00000700 /* interrupt mode 7 */
#define EPSW_IE 0x00000800 /* interrupt enable */
#define EPSW_S 0x00003000 /* software auxiliary bits */
#define EPSW_T 0x00008000 /* trace enable */
#define EPSW_nSL 0x00010000 /* not supervisor level */
#define EPSW_NMID 0x00020000 /* nonmaskable interrupt disable */
#define EPSW_nAR 0x00040000 /* register bank control */
#define EPSW_ML 0x00080000 /* monitor level */
#define EPSW_FE 0x00100000 /* FPU enable */
#define EPSW_IM_SHIFT 8 /* EPSW_IM_SHIFT determines the interrupt mode */
#define NUM2EPSW_IM(num) ((num) << EPSW_IM_SHIFT)
/* FPU registers */
#define FPCR_EF_I 0x00000001 /* inexact result FPU exception flag */
#define FPCR_EF_U 0x00000002 /* underflow FPU exception flag */
#define FPCR_EF_O 0x00000004 /* overflow FPU exception flag */
#define FPCR_EF_Z 0x00000008 /* zero divide FPU exception flag */
#define FPCR_EF_V 0x00000010 /* invalid operand FPU exception flag */
#define FPCR_EE_I 0x00000020 /* inexact result FPU exception enable */
#define FPCR_EE_U 0x00000040 /* underflow FPU exception enable */
#define FPCR_EE_O 0x00000080 /* overflow FPU exception enable */
#define FPCR_EE_Z 0x00000100 /* zero divide FPU exception enable */
#define FPCR_EE_V 0x00000200 /* invalid operand FPU exception enable */
#define FPCR_EC_I 0x00000400 /* inexact result FPU exception cause */
#define FPCR_EC_U 0x00000800 /* underflow FPU exception cause */
#define FPCR_EC_O 0x00001000 /* overflow FPU exception cause */
#define FPCR_EC_Z 0x00002000 /* zero divide FPU exception cause */
#define FPCR_EC_V 0x00004000 /* invalid operand FPU exception cause */
#define FPCR_RM 0x00030000 /* rounding mode */
#define FPCR_RM_NEAREST 0x00000000 /* - round to nearest value */
#define FPCR_FCC_U 0x00040000 /* FPU unordered condition code */
#define FPCR_FCC_E 0x00080000 /* FPU equal condition code */
#define FPCR_FCC_G 0x00100000 /* FPU greater than condition code */
#define FPCR_FCC_L 0x00200000 /* FPU less than condition code */
#define FPCR_INIT 0x00000000 /* no exceptions, rounding to nearest */
/* CPU control registers */
#define CPUP __SYSREG(0xc0000020, u16) /* CPU pipeline register */
#define CPUP_DWBD 0x0020 /* write buffer disable flag */
#define CPUP_IPFD 0x0040 /* instruction prefetch disable flag */
#define CPUP_EXM 0x0080 /* exception operation mode */
#define CPUP_EXM_AM33V1 0x0000 /* - AM33 v1 exception mode */
#define CPUP_EXM_AM33V2 0x0080 /* - AM33 v2 exception mode */
#define CPUM __SYSREG(0xc0000040, u16) /* CPU mode register */
#define CPUM_SLEEP 0x0004 /* set to enter sleep state */
#define CPUM_HALT 0x0008 /* set to enter halt state */
#define CPUM_STOP 0x0010 /* set to enter stop state */
#define CPUREV __SYSREGC(0xc0000050, u32) /* CPU revision register */
#define CPUREV_TYPE 0x0000000f /* CPU type */
#define CPUREV_TYPE_S 0
#define CPUREV_TYPE_AM33_1 0x00000000 /* - AM33-1 core, AM33/1.00 arch */
#define CPUREV_TYPE_AM33_2 0x00000001 /* - AM33-2 core, AM33/2.00 arch */
#define CPUREV_TYPE_AM34_1 0x00000002 /* - AM34-1 core, AM33/2.00 arch */
#define CPUREV_TYPE_AM33_3 0x00000003 /* - AM33-3 core, AM33/2.00 arch */
#define CPUREV_TYPE_AM34_2 0x00000004 /* - AM34-2 core, AM33/3.00 arch */
#define CPUREV_REVISION 0x000000f0 /* CPU revision */
#define CPUREV_REVISION_S 4
#define CPUREV_ICWAY 0x00000f00 /* number of instruction cache ways */
#define CPUREV_ICWAY_S 8
#define CPUREV_ICSIZE 0x0000f000 /* instruction cache way size */
#define CPUREV_ICSIZE_S 12
#define CPUREV_DCWAY 0x000f0000 /* number of data cache ways */
#define CPUREV_DCWAY_S 16
#define CPUREV_DCSIZE 0x00f00000 /* data cache way size */
#define CPUREV_DCSIZE_S 20
#define CPUREV_FPUTYPE 0x0f000000 /* FPU core type */
#define CPUREV_FPUTYPE_NONE 0x00000000 /* - no FPU core implemented */
#define CPUREV_OCDCTG 0xf0000000 /* on-chip debug function category */
#define DCR __SYSREG(0xc0000030, u16) /* Debug control register */
/* interrupt/exception control registers */
#define IVAR0 __SYSREG(0xc0000000, u16) /* interrupt vector 0 */
#define IVAR1 __SYSREG(0xc0000004, u16) /* interrupt vector 1 */
#define IVAR2 __SYSREG(0xc0000008, u16) /* interrupt vector 2 */
#define IVAR3 __SYSREG(0xc000000c, u16) /* interrupt vector 3 */
#define IVAR4 __SYSREG(0xc0000010, u16) /* interrupt vector 4 */
#define IVAR5 __SYSREG(0xc0000014, u16) /* interrupt vector 5 */
#define IVAR6 __SYSREG(0xc0000018, u16) /* interrupt vector 6 */
#define TBR __SYSREG(0xc0000024, u32) /* Trap table base */
#define TBR_TB 0xff000000 /* table base address bits 31-24 */
#define TBR_INT_CODE 0x00ffffff /* interrupt code */
#define DEAR __SYSREG(0xc0000038, u32) /* Data access exception address */
#define sISR __SYSREG(0xc0000044, u32) /* Supervisor interrupt status */
#define sISR_IRQICE 0x00000001 /* ICE interrupt */
#define sISR_ISTEP 0x00000002 /* single step interrupt */
#define sISR_MISSA 0x00000004 /* memory access address misalignment fault */
#define sISR_UNIMP 0x00000008 /* unimplemented instruction execution fault */
#define sISR_PIEXE 0x00000010 /* program interrupt */
#define sISR_MEMERR 0x00000020 /* illegal memory access fault */
#define sISR_IBREAK 0x00000040 /* instraction break interrupt */
#define sISR_DBSRL 0x00000080 /* debug serial interrupt */
#define sISR_PERIDB 0x00000100 /* peripheral debug interrupt */
#define sISR_EXUNIMP 0x00000200 /* unimplemented ex-instruction execution fault */
#define sISR_OBREAK 0x00000400 /* operand break interrupt */
#define sISR_PRIV 0x00000800 /* privileged instruction execution fault */
#define sISR_BUSERR 0x00001000 /* bus error fault */
#define sISR_DBLFT 0x00002000 /* double fault */
#define sISR_DBG 0x00008000 /* debug reserved interrupt */
#define sISR_ITMISS 0x00010000 /* instruction TLB miss */
#define sISR_DTMISS 0x00020000 /* data TLB miss */
#define sISR_ITEX 0x00040000 /* instruction TLB access exception */
#define sISR_DTEX 0x00080000 /* data TLB access exception */
#define sISR_ILGIA 0x00100000 /* illegal instruction access exception */
#define sISR_ILGDA 0x00200000 /* illegal data access exception */
#define sISR_IOIA 0x00400000 /* internal I/O space instruction access excep */
#define sISR_PRIVA 0x00800000 /* privileged space instruction access excep */
#define sISR_PRIDA 0x01000000 /* privileged space data access excep */
#define sISR_DISA 0x02000000 /* data space instruction access excep */
#define sISR_SYSC 0x04000000 /* system call instruction excep */
#define sISR_FPUD 0x08000000 /* FPU disabled excep */
#define sISR_FPUUI 0x10000000 /* FPU unimplemented instruction excep */
#define sISR_FPUOP 0x20000000 /* FPU operation excep */
#define sISR_NE 0x80000000 /* multiple synchronous exceptions excep */
/* cache control registers */
#define CHCTR __SYSREG(0xc0000070, u16) /* cache control */
#define CHCTR_ICEN 0x0001 /* instruction cache enable */
#define CHCTR_DCEN 0x0002 /* data cache enable */
#define CHCTR_ICBUSY 0x0004 /* instruction cache busy */
#define CHCTR_DCBUSY 0x0008 /* data cache busy */
#define CHCTR_ICINV 0x0010 /* instruction cache invalidate */
#define CHCTR_DCINV 0x0020 /* data cache invalidate */
#define CHCTR_DCWTMD 0x0040 /* data cache writing mode */
#define CHCTR_DCWTMD_WRBACK 0x0000 /* - write back mode */
#define CHCTR_DCWTMD_WRTHROUGH 0x0040 /* - write through mode */
#define CHCTR_DCALMD 0x0080 /* data cache allocation mode */
#define CHCTR_ICWMD 0x0f00 /* instruction cache way mode */
#define CHCTR_DCWMD 0xf000 /* data cache way mode */
#ifdef CONFIG_AM34_2
#define ICIVCR __SYSREG(0xc0000c00, u32) /* icache area invalidate control */
#define ICIVCR_ICIVBSY 0x00000008 /* icache area invalidate busy */
#define ICIVCR_ICI 0x00000001 /* icache area invalidate */
#define ICIVMR __SYSREG(0xc0000c04, u32) /* icache area invalidate mask */
#define DCPGCR __SYSREG(0xc0000c10, u32) /* data cache area purge control */
#define DCPGCR_DCPGBSY 0x00000008 /* data cache area purge busy */
#define DCPGCR_DCP 0x00000002 /* data cache area purge */
#define DCPGCR_DCI 0x00000001 /* data cache area invalidate */
#define DCPGMR __SYSREG(0xc0000c14, u32) /* data cache area purge mask */
#endif /* CONFIG_AM34_2 */
/* MMU control registers */
#define MMUCTR __SYSREG(0xc0000090, u32) /* MMU control register */
#define MMUCTR_IRP 0x0000003f /* instruction TLB replace pointer */
#define MMUCTR_ITE 0x00000040 /* instruction TLB enable */
#define MMUCTR_IIV 0x00000080 /* instruction TLB invalidate */
#define MMUCTR_ITL 0x00000700 /* instruction TLB lock pointer */
#define MMUCTR_ITL_NOLOCK 0x00000000 /* - no lock */
#define MMUCTR_ITL_LOCK0 0x00000100 /* - entry 0 locked */
#define MMUCTR_ITL_LOCK0_1 0x00000200 /* - entry 0-1 locked */
#define MMUCTR_ITL_LOCK0_3 0x00000300 /* - entry 0-3 locked */
#define MMUCTR_ITL_LOCK0_7 0x00000400 /* - entry 0-7 locked */
#define MMUCTR_ITL_LOCK0_15 0x00000500 /* - entry 0-15 locked */
#define MMUCTR_CE 0x00008000 /* cacheable bit enable */
#define MMUCTR_DRP 0x003f0000 /* data TLB replace pointer */
#define MMUCTR_DTE 0x00400000 /* data TLB enable */
#define MMUCTR_DIV 0x00800000 /* data TLB invalidate */
#define MMUCTR_DTL 0x07000000 /* data TLB lock pointer */
#define MMUCTR_DTL_NOLOCK 0x00000000 /* - no lock */
#define MMUCTR_DTL_LOCK0 0x01000000 /* - entry 0 locked */
#define MMUCTR_DTL_LOCK0_1 0x02000000 /* - entry 0-1 locked */
#define MMUCTR_DTL_LOCK0_3 0x03000000 /* - entry 0-3 locked */
#define MMUCTR_DTL_LOCK0_7 0x04000000 /* - entry 0-7 locked */
#define MMUCTR_DTL_LOCK0_15 0x05000000 /* - entry 0-15 locked */
#ifdef CONFIG_AM34_2
#define MMUCTR_WTE 0x80000000 /* write-through cache TLB entry bit enable */
#endif
#define PIDR __SYSREG(0xc0000094, u16) /* PID register */
#define PIDR_PID 0x00ff /* process identifier */
#define PTBR __SYSREG(0xc0000098, unsigned long) /* Page table base register */
#define IPTEL __SYSREG(0xc00000a0, u32) /* instruction TLB entry */
#define DPTEL __SYSREG(0xc00000b0, u32) /* data TLB entry */
#define xPTEL_V 0x00000001 /* TLB entry valid */
#define xPTEL_UNUSED1 0x00000002 /* unused bit */
#define xPTEL_UNUSED2 0x00000004 /* unused bit */
#define xPTEL_C 0x00000008 /* cached if set */
#define xPTEL_PV 0x00000010 /* page valid */
#define xPTEL_D 0x00000020 /* dirty */
#define xPTEL_PR 0x000001c0 /* page protection */
#define xPTEL_PR_ROK 0x00000000 /* - R/O kernel */
#define xPTEL_PR_RWK 0x00000100 /* - R/W kernel */
#define xPTEL_PR_ROK_ROU 0x00000080 /* - R/O kernel and R/O user */
#define xPTEL_PR_RWK_ROU 0x00000180 /* - R/W kernel and R/O user */
#define xPTEL_PR_RWK_RWU 0x000001c0 /* - R/W kernel and R/W user */
#define xPTEL_G 0x00000200 /* global (use PID if 0) */
#define xPTEL_PS 0x00000c00 /* page size */
#define xPTEL_PS_4Kb 0x00000000 /* - 4Kb page */
#define xPTEL_PS_128Kb 0x00000400 /* - 128Kb page */
#define xPTEL_PS_1Kb 0x00000800 /* - 1Kb page */
#define xPTEL_PS_4Mb 0x00000c00 /* - 4Mb page */
#define xPTEL_PPN 0xfffff006 /* physical page number */
#define IPTEU __SYSREG(0xc00000a4, u32) /* instruction TLB virtual addr */
#define DPTEU __SYSREG(0xc00000b4, u32) /* data TLB virtual addr */
#define xPTEU_VPN 0xfffffc00 /* virtual page number */
#define xPTEU_PID 0x000000ff /* process identifier to which applicable */
#define IPTEL2 __SYSREG(0xc00000a8, u32) /* instruction TLB entry */
#define DPTEL2 __SYSREG(0xc00000b8, u32) /* data TLB entry */
#define xPTEL2_V 0x00000001 /* TLB entry valid */
#define xPTEL2_C 0x00000002 /* cacheable */
#define xPTEL2_PV 0x00000004 /* page valid */
#define xPTEL2_D 0x00000008 /* dirty */
#define xPTEL2_PR 0x00000070 /* page protection */
#define xPTEL2_PR_ROK 0x00000000 /* - R/O kernel */
#define xPTEL2_PR_RWK 0x00000040 /* - R/W kernel */
#define xPTEL2_PR_ROK_ROU 0x00000020 /* - R/O kernel and R/O user */
#define xPTEL2_PR_RWK_ROU 0x00000060 /* - R/W kernel and R/O user */
#define xPTEL2_PR_RWK_RWU 0x00000070 /* - R/W kernel and R/W user */
#define xPTEL2_G 0x00000080 /* global (use PID if 0) */
#define xPTEL2_PS 0x00000300 /* page size */
#define xPTEL2_PS_4Kb 0x00000000 /* - 4Kb page */
#define xPTEL2_PS_128Kb 0x00000100 /* - 128Kb page */
#define xPTEL2_PS_1Kb 0x00000200 /* - 1Kb page */
#define xPTEL2_PS_4Mb 0x00000300 /* - 4Mb page */
#define xPTEL2_CWT 0x00000400 /* cacheable write-through */
#define xPTEL2_UNUSED1 0x00000800 /* unused bit (broadcast mask) */
#define xPTEL2_PPN 0xfffff000 /* physical page number */
#define xPTEL2_V_BIT 0 /* bit numbers corresponding to above masks */
#define xPTEL2_C_BIT 1
#define xPTEL2_PV_BIT 2
#define xPTEL2_D_BIT 3
#define xPTEL2_G_BIT 7
#define xPTEL2_UNUSED1_BIT 11
#define MMUFCR __SYSREGC(0xc000009c, u32) /* MMU exception cause */
#define MMUFCR_IFC __SYSREGC(0xc000009c, u16) /* MMU instruction excep cause */
#define MMUFCR_DFC __SYSREGC(0xc000009e, u16) /* MMU data exception cause */
#define MMUFCR_xFC_TLBMISS 0x0001 /* TLB miss flag */
#define MMUFCR_xFC_INITWR 0x0002 /* initial write excep flag */
#define MMUFCR_xFC_PGINVAL 0x0004 /* page invalid excep flag */
#define MMUFCR_xFC_PROTVIOL 0x0008 /* protection violation excep flag */
#define MMUFCR_xFC_ACCESS 0x0010 /* access level flag */
#define MMUFCR_xFC_ACCESS_USR 0x0000 /* - user mode */
#define MMUFCR_xFC_ACCESS_SR 0x0010 /* - supervisor mode */
#define MMUFCR_xFC_TYPE 0x0020 /* access type flag */
#define MMUFCR_xFC_TYPE_READ 0x0000 /* - read */
#define MMUFCR_xFC_TYPE_WRITE 0x0020 /* - write */
#define MMUFCR_xFC_PR 0x01c0 /* page protection flag */
#define MMUFCR_xFC_PR_ROK 0x0000 /* - R/O kernel */
#define MMUFCR_xFC_PR_RWK 0x0100 /* - R/W kernel */
#define MMUFCR_xFC_PR_ROK_ROU 0x0080 /* - R/O kernel and R/O user */
#define MMUFCR_xFC_PR_RWK_ROU 0x0180 /* - R/W kernel and R/O user */
#define MMUFCR_xFC_PR_RWK_RWU 0x01c0 /* - R/W kernel and R/W user */
#define MMUFCR_xFC_ILLADDR 0x0200 /* illegal address excep flag */
#ifdef CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
/* atomic operation registers */
#define AAR __SYSREG(0xc0000a00, u32) /* cacheable address */
#define AAR2 __SYSREG(0xc0000a04, u32) /* uncacheable address */
#define ADR __SYSREG(0xc0000a08, u32) /* data */
#define ASR __SYSREG(0xc0000a0c, u32) /* status */
#define AARU __SYSREG(0xd400aa00, u32) /* user address */
#define ADRU __SYSREG(0xd400aa08, u32) /* user data */
#define ASRU __SYSREG(0xd400aa0c, u32) /* user status */
#define ASR_RW 0x00000008 /* read */
#define ASR_BW 0x00000004 /* bus error */
#define ASR_IW 0x00000002 /* interrupt */
#define ASR_LW 0x00000001 /* bus lock */
#define ASRU_RW ASR_RW /* read */
#define ASRU_BW ASR_BW /* bus error */
#define ASRU_IW ASR_IW /* interrupt */
#define ASRU_LW ASR_LW /* bus lock */
/* in inline ASM, we stick the base pointer in to a reg and use offsets from
* it */
#define ATOMIC_OPS_BASE_ADDR 0xc0000a00
#ifndef __ASSEMBLY__
asm(
"_AAR = 0\n"
"_AAR2 = 4\n"
"_ADR = 8\n"
"_ASR = 12\n");
#else
#define _AAR 0
#define _AAR2 4
#define _ADR 8
#define _ASR 12
#endif
/* physical page address for userspace atomic operations registers */
#define USER_ATOMIC_OPS_PAGE_ADDR 0xd400a000
#endif /* CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT */
#endif /* __KERNEL__ */
#endif /* _ASM_CPU_REGS_H */

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arch/mn10300/include/asm/current.h
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/* MN10300 Current task structure accessor
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_CURRENT_H
#define _ASM_CURRENT_H
#include <linux/thread_info.h>
/*
* dedicate E2 to keeping the current task pointer
*/
#ifdef CONFIG_MN10300_CURRENT_IN_E2
register struct task_struct *const current asm("e2") __attribute__((used));
#define get_current() current
extern struct task_struct *__current;
#else
static inline __attribute__((const))
struct task_struct *get_current(void)
{
return current_thread_info()->task;
}
#define current get_current()
#endif
#endif /* _ASM_CURRENT_H */

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arch/mn10300/include/asm/debugger.h
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/* Kernel debugger for MN10300
*
* Copyright (C) 2011 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_DEBUGGER_H
#define _ASM_DEBUGGER_H
#if defined(CONFIG_KERNEL_DEBUGGER)
extern int debugger_intercept(enum exception_code, int, int, struct pt_regs *);
extern int at_debugger_breakpoint(struct pt_regs *);
#ifndef CONFIG_MN10300_DEBUGGER_CACHE_NO_FLUSH
extern void debugger_local_cache_flushinv(void);
extern void debugger_local_cache_flushinv_one(u8 *);
#else
static inline void debugger_local_cache_flushinv(void) {}
static inline void debugger_local_cache_flushinv_one(u8 *addr) {}
#endif
#else /* CONFIG_KERNEL_DEBUGGER */
static inline int debugger_intercept(enum exception_code excep,
int signo, int si_code,
struct pt_regs *regs)
{
return 0;
}
static inline int at_debugger_breakpoint(struct pt_regs *regs)
{
return 0;
}
#endif /* CONFIG_KERNEL_DEBUGGER */
#endif /* _ASM_DEBUGGER_H */

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arch/mn10300/include/asm/delay.h
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/* MN10300 Uninterruptible delay routines
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_DELAY_H
#define _ASM_DELAY_H
extern void __udelay(unsigned long usecs);
extern void __delay(unsigned long loops);
#define udelay(n) __udelay(n)
#endif /* _ASM_DELAY_H */

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arch/mn10300/include/asm/div64.h
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/* MN10300 64-bit division
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_DIV64
#define _ASM_DIV64
#include <linux/types.h>
extern void ____unhandled_size_in_do_div___(void);
/*
* Beginning with gcc 4.6, the MDR register is represented explicitly. We
* must, therefore, at least explicitly clobber the register when we make
* changes to it. The following assembly fragments *could* be rearranged in
* order to leave the moves to/from the MDR register to the compiler, but the
* gains would be minimal at best.
*/
#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6)
# define CLOBBER_MDR_CC "mdr", "cc"
#else
# define CLOBBER_MDR_CC "cc"
#endif
/*
* divide n by base, leaving the result in n and returning the remainder
* - we can do this quite efficiently on the MN10300 by cascading the divides
* through the MDR register
*/
#define do_div(n, base) \
({ \
unsigned __rem = 0; \
if (sizeof(n) <= 4) { \
asm("mov %1,mdr \n" \
"divu %2,%0 \n" \
"mov mdr,%1 \n" \
: "+r"(n), "=d"(__rem) \
: "r"(base), "1"(__rem) \
: CLOBBER_MDR_CC \
); \
} else if (sizeof(n) <= 8) { \
union { \
unsigned long long l; \
u32 w[2]; \
} __quot; \
__quot.l = n; \
asm("mov %0,mdr \n" /* MDR = 0 */ \
"divu %3,%1 \n" \
/* __quot.MSL = __div.MSL / base, */ \
/* MDR = MDR:__div.MSL % base */ \
"divu %3,%2 \n" \
/* __quot.LSL = MDR:__div.LSL / base, */ \
/* MDR = MDR:__div.LSL % base */ \
"mov mdr,%0 \n" \
: "=d"(__rem), "=r"(__quot.w[1]), "=r"(__quot.w[0]) \
: "r"(base), "0"(__rem), "1"(__quot.w[1]), \
"2"(__quot.w[0]) \
: CLOBBER_MDR_CC \
); \
n = __quot.l; \
} else { \
____unhandled_size_in_do_div___(); \
} \
__rem; \
})
/*
* do an unsigned 32-bit multiply and divide with intermediate 64-bit product
* so as not to lose accuracy
* - we use the MDR register to hold the MSW of the product
*/
static inline __attribute__((const))
unsigned __muldiv64u(unsigned val, unsigned mult, unsigned div)
{
unsigned result;
asm("mulu %2,%0 \n" /* MDR:val = val*mult */
"divu %3,%0 \n" /* val = MDR:val/div;
* MDR = MDR:val%div */
: "=r"(result)
: "0"(val), "ir"(mult), "r"(div)
: CLOBBER_MDR_CC
);
return result;
}
/*
* do a signed 32-bit multiply and divide with intermediate 64-bit product so
* as not to lose accuracy
* - we use the MDR register to hold the MSW of the product
*/
static inline __attribute__((const))
signed __muldiv64s(signed val, signed mult, signed div)
{
signed result;
asm("mul %2,%0 \n" /* MDR:val = val*mult */
"div %3,%0 \n" /* val = MDR:val/div;
* MDR = MDR:val%div */
: "=r"(result)
: "0"(val), "ir"(mult), "r"(div)
: CLOBBER_MDR_CC
);
return result;
}
#endif /* _ASM_DIV64 */

21
arch/mn10300/include/asm/dma-mapping.h
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@ -1,21 +0,0 @@
/* DMA mapping routines for the MN10300 arch
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_DMA_MAPPING_H
#define _ASM_DMA_MAPPING_H
extern const struct dma_map_ops mn10300_dma_ops;
static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
{
return &mn10300_dma_ops;
}
#endif

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arch/mn10300/include/asm/dma.h
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@ -1,117 +0,0 @@
/* MN10300 ISA DMA handlers and definitions
*
* Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_DMA_H
#define _ASM_DMA_H
#include <linux/spinlock.h>
#include <asm/io.h>
#include <linux/delay.h>
#undef MAX_DMA_CHANNELS /* switch off linux/kernel/dma.c */
#define MAX_DMA_ADDRESS 0xbfffffff
extern spinlock_t dma_spin_lock;
static inline unsigned long claim_dma_lock(void)
{
unsigned long flags;
spin_lock_irqsave(&dma_spin_lock, flags);
return flags;
}
static inline void release_dma_lock(unsigned long flags)
{
spin_unlock_irqrestore(&dma_spin_lock, flags);
}
/* enable/disable a specific DMA channel */
static inline void enable_dma(unsigned int dmanr)
{
}
static inline void disable_dma(unsigned int dmanr)
{
}
/* Clear the 'DMA Pointer Flip Flop'.
* Write 0 for LSB/MSB, 1 for MSB/LSB access.
* Use this once to initialize the FF to a known state.
* After that, keep track of it. :-)
* --- In order to do that, the DMA routines below should ---
* --- only be used while holding the DMA lock ! ---
*/
static inline void clear_dma_ff(unsigned int dmanr)
{
}
/* set mode (above) for a specific DMA channel */
static inline void set_dma_mode(unsigned int dmanr, char mode)
{
}
/* Set only the page register bits of the transfer address.
* This is used for successive transfers when we know the contents of
* the lower 16 bits of the DMA current address register, but a 64k boundary
* may have been crossed.
*/
static inline void set_dma_page(unsigned int dmanr, char pagenr)
{
}
/* Set transfer address & page bits for specific DMA channel.
* Assumes dma flipflop is clear.
*/
static inline void set_dma_addr(unsigned int dmanr, unsigned int a)
{
}
/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
* a specific DMA channel.
* You must ensure the parameters are valid.
* NOTE: from a manual: "the number of transfers is one more
* than the initial word count"! This is taken into account.
* Assumes dma flip-flop is clear.
* NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
*/
static inline void set_dma_count(unsigned int dmanr, unsigned int count)
{
}
/* Get DMA residue count. After a DMA transfer, this
* should return zero. Reading this while a DMA transfer is
* still in progress will return unpredictable results.
* If called before the channel has been used, it may return 1.
* Otherwise, it returns the number of _bytes_ left to transfer.
*
* Assumes DMA flip-flop is clear.
*/
static inline int get_dma_residue(unsigned int dmanr)
{
return 0;
}
/* These are in kernel/dma.c: */
extern int request_dma(unsigned int dmanr, const char *device_id);
extern void free_dma(unsigned int dmanr);
/* From PCI */
#ifdef CONFIG_PCI
extern int isa_dma_bridge_buggy;
#else
#define isa_dma_bridge_buggy (0)
#endif
#endif /* _ASM_DMA_H */

16
arch/mn10300/include/asm/dmactl-regs.h
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@ -1,16 +0,0 @@
/* MN10300 on-board DMA controller registers
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_DMACTL_REGS_H
#define _ASM_DMACTL_REGS_H
#include <proc/dmactl-regs.h>
#endif /* _ASM_DMACTL_REGS_H */

153
arch/mn10300/include/asm/elf.h
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/* MN10300 ELF constant and register definitions
*
* Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_ELF_H
#define _ASM_ELF_H
#include <linux/utsname.h>
#include <asm/ptrace.h>
#include <asm/user.h>
/*
* AM33 relocations
*/
#define R_MN10300_NONE 0 /* No reloc. */
#define R_MN10300_32 1 /* Direct 32 bit. */
#define R_MN10300_16 2 /* Direct 16 bit. */
#define R_MN10300_8 3 /* Direct 8 bit. */
#define R_MN10300_PCREL32 4 /* PC-relative 32-bit. */
#define R_MN10300_PCREL16 5 /* PC-relative 16-bit signed. */
#define R_MN10300_PCREL8 6 /* PC-relative 8-bit signed. */
#define R_MN10300_24 9 /* Direct 24 bit. */
#define R_MN10300_RELATIVE 23 /* Adjust by program base. */
#define R_MN10300_SYM_DIFF 33 /* Adjustment when relaxing. */
#define R_MN10300_ALIGN 34 /* Alignment requirement. */
/*
* AM33/AM34 HW Capabilities
*/
#define HWCAP_MN10300_ATOMIC_OP_UNIT 1 /* Has AM34 Atomic Operations */
/*
* ELF register definitions..
*/
typedef unsigned long elf_greg_t;
#define ELF_NGREG ((sizeof(struct pt_regs) / sizeof(elf_greg_t)) - 1)
typedef elf_greg_t elf_gregset_t[ELF_NGREG];
#define ELF_NFPREG 32
typedef float elf_fpreg_t;
typedef struct {
elf_fpreg_t fpregs[ELF_NFPREG];
u_int32_t fpcr;
} elf_fpregset_t;
/*
* This is used to ensure we don't load something for the wrong architecture
*/
#define elf_check_arch(x) \
(((x)->e_machine == EM_CYGNUS_MN10300) || \
((x)->e_machine == EM_MN10300))
/*
* These are used to set parameters in the core dumps.
*/
#define ELF_CLASS ELFCLASS32
#define ELF_DATA ELFDATA2LSB
#define ELF_ARCH EM_MN10300
/*
* ELF process initialiser
*/
#define ELF_PLAT_INIT(_r, load_addr) \
do { \
struct pt_regs *_ur = current->thread.uregs; \
_ur->a3 = 0; _ur->a2 = 0; _ur->d3 = 0; _ur->d2 = 0; \
_ur->mcvf = 0; _ur->mcrl = 0; _ur->mcrh = 0; _ur->mdrq = 0; \
_ur->e1 = 0; _ur->e0 = 0; _ur->e7 = 0; _ur->e6 = 0; \
_ur->e5 = 0; _ur->e4 = 0; _ur->e3 = 0; _ur->e2 = 0; \
_ur->lar = 0; _ur->lir = 0; _ur->mdr = 0; \
_ur->a1 = 0; _ur->a0 = 0; _ur->d1 = 0; _ur->d0 = 0; \
} while (0)
#define CORE_DUMP_USE_REGSET
#define ELF_EXEC_PAGESIZE 4096
/*
* This is the location that an ET_DYN program is loaded if exec'ed. Typical
* use of this is to invoke "./ld.so someprog" to test out a new version of
* the loader. We need to make sure that it is out of the way of the program
* that it will "exec", and that there is sufficient room for the brk.
* - must clear the VMALLOC area
*/
#define ELF_ET_DYN_BASE 0x04000000
/*
* regs is struct pt_regs, pr_reg is elf_gregset_t (which is
* now struct user_regs, they are different)
* - ELF_CORE_COPY_REGS has been guessed, and may be wrong
*/
#define ELF_CORE_COPY_REGS(pr_reg, regs) \
do { \
pr_reg[0] = regs->a3; \
pr_reg[1] = regs->a2; \
pr_reg[2] = regs->d3; \
pr_reg[3] = regs->d2; \
pr_reg[4] = regs->mcvf; \
pr_reg[5] = regs->mcrl; \
pr_reg[6] = regs->mcrh; \
pr_reg[7] = regs->mdrq; \
pr_reg[8] = regs->e1; \
pr_reg[9] = regs->e0; \
pr_reg[10] = regs->e7; \
pr_reg[11] = regs->e6; \
pr_reg[12] = regs->e5; \
pr_reg[13] = regs->e4; \
pr_reg[14] = regs->e3; \
pr_reg[15] = regs->e2; \
pr_reg[16] = regs->sp; \
pr_reg[17] = regs->lar; \
pr_reg[18] = regs->lir; \
pr_reg[19] = regs->mdr; \
pr_reg[20] = regs->a1; \
pr_reg[21] = regs->a0; \
pr_reg[22] = regs->d1; \
pr_reg[23] = regs->d0; \
pr_reg[24] = regs->orig_d0; \
pr_reg[25] = regs->epsw; \
pr_reg[26] = regs->pc; \
} while (0);
/*
* This yields a mask that user programs can use to figure out what
* instruction set this CPU supports. This could be done in user space,
* but it's not easy, and we've already done it here.
*/
#ifdef CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
#define ELF_HWCAP (HWCAP_MN10300_ATOMIC_OP_UNIT)
#else
#define ELF_HWCAP (0)
#endif
/*
* This yields a string that ld.so will use to load implementation
* specific libraries for optimization. This is more specific in
* intent than poking at uname or /proc/cpuinfo.
*
* For the moment, we have only optimizations for the Intel generations,
* but that could change...
*/
#define ELF_PLATFORM (NULL)
#endif /* _ASM_ELF_H */

1
arch/mn10300/include/asm/emergency-restart.h
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#include <asm-generic/emergency-restart.h>

121
arch/mn10300/include/asm/exceptions.h
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@ -1,121 +0,0 @@
/* MN10300 Microcontroller core exceptions
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_EXCEPTIONS_H
#define _ASM_EXCEPTIONS_H
#include <linux/linkage.h>
/*
* define the breakpoint instruction opcode to use
* - note that the JTAG unit steals 0xFF, so you can't use JTAG and GDBSTUB at
* the same time.
*/
#define GDBSTUB_BKPT 0xFF
#ifndef __ASSEMBLY__
/*
* enumeration of exception codes (as extracted from TBR MSW)
*/
enum exception_code {
EXCEP_RESET = 0x000000, /* reset */
/* MMU exceptions */
EXCEP_ITLBMISS = 0x000100, /* instruction TLB miss */
EXCEP_DTLBMISS = 0x000108, /* data TLB miss */
EXCEP_IAERROR = 0x000110, /* instruction address */
EXCEP_DAERROR = 0x000118, /* data address */
/* system exceptions */
EXCEP_TRAP = 0x000128, /* program interrupt (PI instruction) */
EXCEP_ISTEP = 0x000130, /* single step */
EXCEP_IBREAK = 0x000150, /* instruction breakpoint */
EXCEP_OBREAK = 0x000158, /* operand breakpoint */
EXCEP_PRIVINS = 0x000160, /* privileged instruction execution */
EXCEP_UNIMPINS = 0x000168, /* unimplemented instruction execution */
EXCEP_UNIMPEXINS = 0x000170, /* unimplemented extended instruction execution */
EXCEP_MEMERR = 0x000178, /* illegal memory access */
EXCEP_MISALIGN = 0x000180, /* misalignment */
EXCEP_BUSERROR = 0x000188, /* bus error */
EXCEP_ILLINSACC = 0x000190, /* illegal instruction access */
EXCEP_ILLDATACC = 0x000198, /* illegal data access */
EXCEP_IOINSACC = 0x0001a0, /* I/O space instruction access */
EXCEP_PRIVINSACC = 0x0001a8, /* privileged space instruction access */
EXCEP_PRIVDATACC = 0x0001b0, /* privileged space data access */
EXCEP_DATINSACC = 0x0001b8, /* data space instruction access */
EXCEP_DOUBLE_FAULT = 0x000200, /* double fault */
/* FPU exceptions */
EXCEP_FPU_DISABLED = 0x0001c0, /* FPU disabled */
EXCEP_FPU_UNIMPINS = 0x0001c8, /* FPU unimplemented operation */
EXCEP_FPU_OPERATION = 0x0001d0, /* FPU operation */
/* interrupts */
EXCEP_WDT = 0x000240, /* watchdog timer overflow */
EXCEP_NMI = 0x000248, /* non-maskable interrupt */
EXCEP_IRQ_LEVEL0 = 0x000280, /* level 0 maskable interrupt */
EXCEP_IRQ_LEVEL1 = 0x000288, /* level 1 maskable interrupt */
EXCEP_IRQ_LEVEL2 = 0x000290, /* level 2 maskable interrupt */
EXCEP_IRQ_LEVEL3 = 0x000298, /* level 3 maskable interrupt */
EXCEP_IRQ_LEVEL4 = 0x0002a0, /* level 4 maskable interrupt */
EXCEP_IRQ_LEVEL5 = 0x0002a8, /* level 5 maskable interrupt */
EXCEP_IRQ_LEVEL6 = 0x0002b0, /* level 6 maskable interrupt */
/* system calls */
EXCEP_SYSCALL0 = 0x000300, /* system call 0 */
EXCEP_SYSCALL1 = 0x000308, /* system call 1 */
EXCEP_SYSCALL2 = 0x000310, /* system call 2 */
EXCEP_SYSCALL3 = 0x000318, /* system call 3 */
EXCEP_SYSCALL4 = 0x000320, /* system call 4 */
EXCEP_SYSCALL5 = 0x000328, /* system call 5 */
EXCEP_SYSCALL6 = 0x000330, /* system call 6 */
EXCEP_SYSCALL7 = 0x000338, /* system call 7 */
EXCEP_SYSCALL8 = 0x000340, /* system call 8 */
EXCEP_SYSCALL9 = 0x000348, /* system call 9 */
EXCEP_SYSCALL10 = 0x000350, /* system call 10 */
EXCEP_SYSCALL11 = 0x000358, /* system call 11 */
EXCEP_SYSCALL12 = 0x000360, /* system call 12 */
EXCEP_SYSCALL13 = 0x000368, /* system call 13 */
EXCEP_SYSCALL14 = 0x000370, /* system call 14 */
EXCEP_SYSCALL15 = 0x000378, /* system call 15 */
};
extern void __set_intr_stub(enum exception_code code, void *handler);
extern void set_intr_stub(enum exception_code code, void *handler);
struct pt_regs;
extern asmlinkage void __common_exception(void);
extern asmlinkage void itlb_miss(void);
extern asmlinkage void dtlb_miss(void);
extern asmlinkage void itlb_aerror(void);
extern asmlinkage void dtlb_aerror(void);
extern asmlinkage void raw_bus_error(void);
extern asmlinkage void double_fault(void);
extern asmlinkage int system_call(struct pt_regs *);
extern asmlinkage void nmi(struct pt_regs *, enum exception_code);
extern asmlinkage void uninitialised_exception(struct pt_regs *,
enum exception_code);
extern asmlinkage void irq_handler(void);
extern asmlinkage void profile_handler(void);
extern asmlinkage void nmi_handler(void);
extern asmlinkage void misalignment(struct pt_regs *, enum exception_code);
extern void die(const char *, struct pt_regs *, enum exception_code)
__noreturn;
extern int die_if_no_fixup(const char *, struct pt_regs *, enum exception_code);
#define NUM2EXCEP_IRQ_LEVEL(num) (EXCEP_IRQ_LEVEL0 + (num) * 8)
#endif /* __ASSEMBLY__ */
#endif /* _ASM_EXCEPTIONS_H */

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arch/mn10300/include/asm/fpu.h
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/* MN10300 FPU definitions
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
* Derived from include/asm-i386/i387.h: Copyright (C) 1994 Linus Torvalds
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_FPU_H
#define _ASM_FPU_H
#ifndef __ASSEMBLY__
#include <linux/sched.h>
#include <asm/exceptions.h>
#include <asm/sigcontext.h>
#ifdef __KERNEL__
extern asmlinkage void fpu_disabled(void);
#ifdef CONFIG_FPU
#ifdef CONFIG_LAZY_SAVE_FPU
/* the task that currently owns the FPU state */
extern struct task_struct *fpu_state_owner;
#endif
#if (THREAD_USING_FPU & ~0xff)
#error THREAD_USING_FPU must be smaller than 0x100.
#endif
static inline void set_using_fpu(struct task_struct *tsk)
{
asm volatile(
"bset %0,(0,%1)"
:
: "i"(THREAD_USING_FPU), "a"(&tsk->thread.fpu_flags)
: "memory", "cc");
}
static inline void clear_using_fpu(struct task_struct *tsk)
{
asm volatile(
"bclr %0,(0,%1)"
:
: "i"(THREAD_USING_FPU), "a"(&tsk->thread.fpu_flags)
: "memory", "cc");
}
#define is_using_fpu(tsk) ((tsk)->thread.fpu_flags & THREAD_USING_FPU)
extern asmlinkage void fpu_kill_state(struct task_struct *);
extern asmlinkage void fpu_exception(struct pt_regs *, enum exception_code);
extern asmlinkage void fpu_init_state(void);
extern asmlinkage void fpu_save(struct fpu_state_struct *);
extern int fpu_setup_sigcontext(struct fpucontext *buf);
extern int fpu_restore_sigcontext(struct fpucontext *buf);
static inline void unlazy_fpu(struct task_struct *tsk)
{
preempt_disable();
#ifndef CONFIG_LAZY_SAVE_FPU
if (tsk->thread.fpu_flags & THREAD_HAS_FPU) {
fpu_save(&tsk->thread.fpu_state);
tsk->thread.fpu_flags &= ~THREAD_HAS_FPU;
tsk->thread.uregs->epsw &= ~EPSW_FE;
}
#else
if (fpu_state_owner == tsk)
fpu_save(&tsk->thread.fpu_state);
#endif
preempt_enable();
}
static inline void exit_fpu(struct task_struct *tsk)
{
#ifdef CONFIG_LAZY_SAVE_FPU
preempt_disable();
if (fpu_state_owner == tsk)
fpu_state_owner = NULL;
preempt_enable();
#endif
}
static inline void flush_fpu(void)
{
struct task_struct *tsk = current;
preempt_disable();
#ifndef CONFIG_LAZY_SAVE_FPU
if (tsk->thread.fpu_flags & THREAD_HAS_FPU) {
tsk->thread.fpu_flags &= ~THREAD_HAS_FPU;
tsk->thread.uregs->epsw &= ~EPSW_FE;
}
#else
if (fpu_state_owner == tsk) {
fpu_state_owner = NULL;
tsk->thread.uregs->epsw &= ~EPSW_FE;
}
#endif
preempt_enable();
clear_using_fpu(tsk);
}
#else /* CONFIG_FPU */
extern asmlinkage
void unexpected_fpu_exception(struct pt_regs *, enum exception_code);
#define fpu_exception unexpected_fpu_exception
struct task_struct;
struct fpu_state_struct;
static inline bool is_using_fpu(struct task_struct *tsk) { return false; }
static inline void set_using_fpu(struct task_struct *tsk) {}
static inline void clear_using_fpu(struct task_struct *tsk) {}
static inline void fpu_init_state(void) {}
static inline void fpu_save(struct fpu_state_struct *s) {}
static inline void fpu_kill_state(struct task_struct *tsk) {}
static inline void unlazy_fpu(struct task_struct *tsk) {}
static inline void exit_fpu(struct task_struct *tsk) {}
static inline void flush_fpu(void) {}
static inline int fpu_setup_sigcontext(struct fpucontext *buf) { return 0; }
static inline int fpu_restore_sigcontext(struct fpucontext *buf) { return 0; }
#endif /* CONFIG_FPU */
#endif /* __KERNEL__ */
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_FPU_H */

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arch/mn10300/include/asm/frame.inc
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/* MN10300 Microcontroller core system register definitions -*- asm -*-
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_FRAME_INC
#define _ASM_FRAME_INC
#ifndef __ASSEMBLY__
#error not for use in C files
#endif
#ifndef __ASM_OFFSETS_H__
#include <asm/asm-offsets.h>
#endif
#include <asm/thread_info.h>
#define pi break
#define fp a3
###############################################################################
#
# build a stack frame from the registers
# - the caller has subtracted 4 from SP before coming here
#
###############################################################################
.macro SAVE_ALL
add -4,sp # next exception frame ptr save area
movm [other],(sp)
mov usp,a1
mov a1,(sp) # USP in MOVM[other] dummy slot
movm [d2,d3,a2,a3,exreg0,exreg1,exother],(sp)
mov sp,fp # FRAME pointer in A3
add -12,sp # allow for calls to be made
# push the exception frame onto the front of the list
GET_THREAD_INFO a1
mov (TI_frame,a1),a0
mov a0,(REG_NEXT,fp)
mov fp,(TI_frame,a1)
# disable the FPU inside the kernel
and ~EPSW_FE,epsw
# we may be holding current in E2
#ifdef CONFIG_MN10300_CURRENT_IN_E2
mov (__current),e2
#endif
.endm
###############################################################################
#
# restore the registers from a stack frame
#
###############################################################################
.macro RESTORE_ALL
# peel back the stack to the calling frame
# - we need that when returning from interrupts to kernel mode
GET_THREAD_INFO a0
mov (TI_frame,a0),fp
mov fp,sp
mov (REG_NEXT,fp),d0
mov d0,(TI_frame,a0) # userspace has regs->next == 0
#ifndef CONFIG_MN10300_USING_JTAG
mov (REG_EPSW,fp),d0
btst EPSW_T,d0
beq 99f
or EPSW_NMID,epsw
movhu (DCR),d1
or 0x0001, d1
movhu d1,(DCR)
99:
#endif
movm (sp),[d2,d3,a2,a3,exreg0,exreg1,exother]
# must restore usp even if returning to kernel space,
# when CONFIG_PREEMPT is enabled.
mov (sp),a1 # USP in MOVM[other] dummy slot
mov a1,usp
movm (sp),[other]
add 8,sp
rti
.endm
#endif /* _ASM_FRAME_INC */

1
arch/mn10300/include/asm/ftrace.h
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/* empty */

1
arch/mn10300/include/asm/futex.h
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#include <asm-generic/futex.h>

182
arch/mn10300/include/asm/gdb-stub.h
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/* MN10300 Kernel GDB stub definitions
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
* - Derived from asm-mips/gdb-stub.h (c) 1995 Andreas Busse
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_GDB_STUB_H
#define _ASM_GDB_STUB_H
#include <asm/exceptions.h>
/*
* register ID numbers in GDB remote protocol
*/
#define GDB_REGID_PC 9
#define GDB_REGID_FP 7
#define GDB_REGID_SP 8
/*
* virtual stack layout for the GDB exception handler
*/
#define NUMREGS 64
#define GDB_FR_D0 (0 * 4)
#define GDB_FR_D1 (1 * 4)
#define GDB_FR_D2 (2 * 4)
#define GDB_FR_D3 (3 * 4)
#define GDB_FR_A0 (4 * 4)
#define GDB_FR_A1 (5 * 4)
#define GDB_FR_A2 (6 * 4)
#define GDB_FR_A3 (7 * 4)
#define GDB_FR_SP (8 * 4)
#define GDB_FR_PC (9 * 4)
#define GDB_FR_MDR (10 * 4)
#define GDB_FR_EPSW (11 * 4)
#define GDB_FR_LIR (12 * 4)
#define GDB_FR_LAR (13 * 4)
#define GDB_FR_MDRQ (14 * 4)
#define GDB_FR_E0 (15 * 4)
#define GDB_FR_E1 (16 * 4)
#define GDB_FR_E2 (17 * 4)
#define GDB_FR_E3 (18 * 4)
#define GDB_FR_E4 (19 * 4)
#define GDB_FR_E5 (20 * 4)
#define GDB_FR_E6 (21 * 4)
#define GDB_FR_E7 (22 * 4)
#define GDB_FR_SSP (23 * 4)
#define GDB_FR_MSP (24 * 4)
#define GDB_FR_USP (25 * 4)
#define GDB_FR_MCRH (26 * 4)
#define GDB_FR_MCRL (27 * 4)
#define GDB_FR_MCVF (28 * 4)
#define GDB_FR_FPCR (29 * 4)
#define GDB_FR_DUMMY0 (30 * 4)
#define GDB_FR_DUMMY1 (31 * 4)
#define GDB_FR_FS0 (32 * 4)
#define GDB_FR_SIZE (NUMREGS * 4)
#ifndef __ASSEMBLY__
/*
* This is the same as above, but for the high-level
* part of the GDB stub.
*/
struct gdb_regs {
/* saved main processor registers */
u32 d0, d1, d2, d3, a0, a1, a2, a3;
u32 sp, pc, mdr, epsw, lir, lar, mdrq;
u32 e0, e1, e2, e3, e4, e5, e6, e7;
u32 ssp, msp, usp, mcrh, mcrl, mcvf;
/* saved floating point registers */
u32 fpcr, _dummy0, _dummy1;
u32 fs0, fs1, fs2, fs3, fs4, fs5, fs6, fs7;
u32 fs8, fs9, fs10, fs11, fs12, fs13, fs14, fs15;
u32 fs16, fs17, fs18, fs19, fs20, fs21, fs22, fs23;
u32 fs24, fs25, fs26, fs27, fs28, fs29, fs30, fs31;
};
/*
* Prototypes
*/
extern void show_registers_only(struct pt_regs *regs);
extern asmlinkage void gdbstub_init(void);
extern asmlinkage void gdbstub_exit(int status);
extern asmlinkage void gdbstub_io_init(void);
extern asmlinkage void gdbstub_io_set_baud(unsigned baud);
extern asmlinkage int gdbstub_io_rx_char(unsigned char *_ch, int nonblock);
extern asmlinkage void gdbstub_io_tx_char(unsigned char ch);
extern asmlinkage void gdbstub_io_tx_flush(void);
extern asmlinkage void gdbstub_io_rx_handler(void);
extern asmlinkage void gdbstub_rx_irq(struct pt_regs *, enum exception_code);
extern asmlinkage int gdbstub_intercept(struct pt_regs *, enum exception_code);
extern asmlinkage void gdbstub_exception(struct pt_regs *, enum exception_code);
extern asmlinkage void __gdbstub_bug_trap(void);
extern asmlinkage void __gdbstub_pause(void);
#ifdef CONFIG_MN10300_CACHE_ENABLED
extern asmlinkage void gdbstub_purge_cache(void);
#else
#define gdbstub_purge_cache() do {} while (0)
#endif
/* Used to prevent crashes in memory access */
extern asmlinkage int gdbstub_read_byte(const u8 *, u8 *);
extern asmlinkage int gdbstub_read_word(const u8 *, u8 *);
extern asmlinkage int gdbstub_read_dword(const u8 *, u8 *);
extern asmlinkage int gdbstub_write_byte(u32, u8 *);
extern asmlinkage int gdbstub_write_word(u32, u8 *);
extern asmlinkage int gdbstub_write_dword(u32, u8 *);
extern asmlinkage void gdbstub_read_byte_guard(void);
extern asmlinkage void gdbstub_read_byte_cont(void);
extern asmlinkage void gdbstub_read_word_guard(void);
extern asmlinkage void gdbstub_read_word_cont(void);
extern asmlinkage void gdbstub_read_dword_guard(void);
extern asmlinkage void gdbstub_read_dword_cont(void);
extern asmlinkage void gdbstub_write_byte_guard(void);
extern asmlinkage void gdbstub_write_byte_cont(void);
extern asmlinkage void gdbstub_write_word_guard(void);
extern asmlinkage void gdbstub_write_word_cont(void);
extern asmlinkage void gdbstub_write_dword_guard(void);
extern asmlinkage void gdbstub_write_dword_cont(void);
extern u8 gdbstub_rx_buffer[PAGE_SIZE];
extern u32 gdbstub_rx_inp;
extern u32 gdbstub_rx_outp;
extern u8 gdbstub_rx_overflow;
extern u8 gdbstub_busy;
extern u8 gdbstub_rx_unget;
#ifdef CONFIG_GDBSTUB_DEBUGGING
extern void gdbstub_printk(const char *fmt, ...)
__attribute__((format(printf, 1, 2)));
#else
static inline __attribute__((format(printf, 1, 2)))
void gdbstub_printk(const char *fmt, ...)
{
}
#endif
#ifdef CONFIG_GDBSTUB_DEBUG_ENTRY
#define gdbstub_entry(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__)
#else
#define gdbstub_entry(FMT, ...) no_printk(FMT, ##__VA_ARGS__)
#endif
#ifdef CONFIG_GDBSTUB_DEBUG_PROTOCOL
#define gdbstub_proto(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__)
#else
#define gdbstub_proto(FMT, ...) no_printk(FMT, ##__VA_ARGS__)
#endif
#ifdef CONFIG_GDBSTUB_DEBUG_IO
#define gdbstub_io(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__)
#else
#define gdbstub_io(FMT, ...) no_printk(FMT, ##__VA_ARGS__)
#endif
#ifdef CONFIG_GDBSTUB_DEBUG_BREAKPOINT
#define gdbstub_bkpt(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__)
#else
#define gdbstub_bkpt(FMT, ...) no_printk(FMT, ##__VA_ARGS__)
#endif
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_GDB_STUB_H */

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arch/mn10300/include/asm/hardirq.h
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/* MN10300 Hardware IRQ statistics and management
*
* Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Modified by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_HARDIRQ_H
#define _ASM_HARDIRQ_H
#include <linux/threads.h>
#include <linux/irq.h>
#include <asm/exceptions.h>
/* assembly code in softirq.h is sensitive to the offsets of these fields */
typedef struct {
unsigned int __softirq_pending;
#ifdef CONFIG_MN10300_WD_TIMER
unsigned int __nmi_count; /* arch dependent */
unsigned int __irq_count; /* arch dependent */
#endif
} ____cacheline_aligned irq_cpustat_t;
#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
extern void ack_bad_irq(int irq);
/*
* manipulate stubs in the MN10300 CPU Trap/Interrupt Vector table
* - these should jump to __common_exception in entry.S unless there's a good
* reason to do otherwise (see trap_preinit() in traps.c)
*/
typedef void (*intr_stub_fnx)(struct pt_regs *regs,
enum exception_code intcode);
/*
* manipulate pointers in the Exception table (see entry.S)
* - these are indexed by decoding the lower 24 bits of the TBR register
* - note that the MN103E010 doesn't always trap through the correct vector,
* but does always set the TBR correctly
*/
extern asmlinkage void set_excp_vector(enum exception_code code,
intr_stub_fnx handler);
#endif /* _ASM_HARDIRQ_H */

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arch/mn10300/include/asm/highmem.h
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/* MN10300 Virtual kernel memory mappings for high memory
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
* - Derived from include/asm-i386/highmem.h
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_HIGHMEM_H
#define _ASM_HIGHMEM_H
#ifdef __KERNEL__
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/highmem.h>
#include <asm/kmap_types.h>
#include <asm/pgtable.h>
/* undef for production */
#undef HIGHMEM_DEBUG
/* declarations for highmem.c */
extern unsigned long highstart_pfn, highend_pfn;
extern pte_t *kmap_pte;
extern pgprot_t kmap_prot;
extern pte_t *pkmap_page_table;
extern void __init kmap_init(void);
/*
* Right now we initialize only a single pte table. It can be extended
* easily, subsequent pte tables have to be allocated in one physical
* chunk of RAM.
*/
#define PKMAP_BASE 0xfe000000UL
#define LAST_PKMAP 1024
#define LAST_PKMAP_MASK (LAST_PKMAP - 1)
#define PKMAP_NR(virt) ((virt - PKMAP_BASE) >> PAGE_SHIFT)
#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
extern unsigned long kmap_high(struct page *page);
extern void kunmap_high(struct page *page);
static inline unsigned long kmap(struct page *page)
{
if (in_interrupt())
BUG();
if (page < highmem_start_page)
return page_address(page);
return kmap_high(page);
}
static inline void kunmap(struct page *page)
{
if (in_interrupt())
BUG();
if (page < highmem_start_page)
return;
kunmap_high(page);
}
/*
* The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap
* gives a more generic (and caching) interface. But kmap_atomic can
* be used in IRQ contexts, so in some (very limited) cases we need
* it.
*/
static inline void *kmap_atomic(struct page *page)
{
unsigned long vaddr;
int idx, type;
preempt_disable();
pagefault_disable();
if (page < highmem_start_page)
return page_address(page);
type = kmap_atomic_idx_push();
idx = type + KM_TYPE_NR * smp_processor_id();
vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
#if HIGHMEM_DEBUG
if (!pte_none(*(kmap_pte - idx)))
BUG();
#endif
set_pte(kmap_pte - idx, mk_pte(page, kmap_prot));
local_flush_tlb_one(vaddr);
return (void *)vaddr;
}
static inline void __kunmap_atomic(unsigned long vaddr)
{
int type;
if (vaddr < FIXADDR_START) { /* FIXME */
pagefault_enable();
preempt_enable();
return;
}
type = kmap_atomic_idx();
#if HIGHMEM_DEBUG
{
unsigned int idx;
idx = type + KM_TYPE_NR * smp_processor_id();
if (vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx))
BUG();
/*
* force other mappings to Oops if they'll try to access
* this pte without first remap it
*/
pte_clear(kmap_pte - idx);
local_flush_tlb_one(vaddr);
}
#endif
kmap_atomic_idx_pop();
pagefault_enable();
preempt_enable();
}
#endif /* __KERNEL__ */
#endif /* _ASM_HIGHMEM_H */

14
arch/mn10300/include/asm/hw_irq.h
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/* MN10300 Hardware interrupt definitions
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_HW_IRQ_H
#define _ASM_HW_IRQ_H
#endif /* _ASM_HW_IRQ_H */

71
arch/mn10300/include/asm/intctl-regs.h
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/* MN10300 On-board interrupt controller registers
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_INTCTL_REGS_H
#define _ASM_INTCTL_REGS_H
#include <asm/cpu-regs.h>
#ifdef __KERNEL__
/*
* Interrupt controller registers
* - Registers 64-191 are at addresses offset from the main array
*/
#define GxICR(X) \
__SYSREG(0xd4000000 + (X) * 4 + \
(((X) >= 64) && ((X) < 192)) * 0xf00, u16)
#define GxICR_u8(X) \
__SYSREG(0xd4000000 + (X) * 4 + \
(((X) >= 64) && ((X) < 192)) * 0xf00, u8)
#include <proc/intctl-regs.h>
#define XIRQ_TRIGGER_LOWLEVEL 0
#define XIRQ_TRIGGER_HILEVEL 1
#define XIRQ_TRIGGER_NEGEDGE 2
#define XIRQ_TRIGGER_POSEDGE 3
/* non-maskable interrupt control */
#define NMIIRQ 0
#define NMICR GxICR(NMIIRQ) /* NMI control register */
#define NMICR_NMIF 0x0001 /* NMI pin interrupt flag */
#define NMICR_WDIF 0x0002 /* watchdog timer overflow flag */
#define NMICR_ABUSERR 0x0008 /* async bus error flag */
/* maskable interrupt control */
#define GxICR_DETECT 0x0001 /* interrupt detect flag */
#define GxICR_REQUEST 0x0010 /* interrupt request flag */
#define GxICR_ENABLE 0x0100 /* interrupt enable flag */
#define GxICR_LEVEL 0x7000 /* interrupt priority level */
#define GxICR_LEVEL_0 0x0000 /* - level 0 */
#define GxICR_LEVEL_1 0x1000 /* - level 1 */
#define GxICR_LEVEL_2 0x2000 /* - level 2 */
#define GxICR_LEVEL_3 0x3000 /* - level 3 */
#define GxICR_LEVEL_4 0x4000 /* - level 4 */
#define GxICR_LEVEL_5 0x5000 /* - level 5 */
#define GxICR_LEVEL_6 0x6000 /* - level 6 */
#define GxICR_LEVEL_SHIFT 12
#define GxICR_NMI 0x8000 /* nmi request flag */
#define NUM2GxICR_LEVEL(num) ((num) << GxICR_LEVEL_SHIFT)
#ifndef __ASSEMBLY__
extern void set_intr_level(int irq, u16 level);
extern void mn10300_set_lateack_irq_type(int irq);
#endif
/* external interrupts */
#define XIRQxICR(X) GxICR((X)) /* external interrupt control regs */
#endif /* __KERNEL__ */
#endif /* _ASM_INTCTL_REGS_H */

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arch/mn10300/include/asm/io.h
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/* MN10300 I/O port emulation and memory-mapped I/O
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_IO_H
#define _ASM_IO_H
#include <asm/page.h> /* I/O is all done through memory accesses */
#include <asm/cpu-regs.h>
#include <asm/cacheflush.h>
#include <asm-generic/pci_iomap.h>
#define mmiowb() do {} while (0)
/*****************************************************************************/
/*
* readX/writeX() are used to access memory mapped devices. On some
* architectures the memory mapped IO stuff needs to be accessed
* differently. On the x86 architecture, we just read/write the
* memory location directly.
*/
static inline u8 readb(const volatile void __iomem *addr)
{
return *(const volatile u8 *) addr;
}
static inline u16 readw(const volatile void __iomem *addr)
{
return *(const volatile u16 *) addr;
}
static inline u32 readl(const volatile void __iomem *addr)
{
return *(const volatile u32 *) addr;
}
#define __raw_readb readb
#define __raw_readw readw
#define __raw_readl readl
#define readb_relaxed readb
#define readw_relaxed readw
#define readl_relaxed readl
static inline void writeb(u8 b, volatile void __iomem *addr)
{
*(volatile u8 *) addr = b;
}
static inline void writew(u16 b, volatile void __iomem *addr)
{
*(volatile u16 *) addr = b;
}
static inline void writel(u32 b, volatile void __iomem *addr)
{
*(volatile u32 *) addr = b;
}
#define __raw_writeb writeb
#define __raw_writew writew
#define __raw_writel writel
#define writeb_relaxed writeb
#define writew_relaxed writew
#define writel_relaxed writel
/*****************************************************************************/
/*
* traditional input/output functions
*/
static inline u8 inb_local(unsigned long addr)
{
return readb((volatile void __iomem *) addr);
}
static inline void outb_local(u8 b, unsigned long addr)
{
return writeb(b, (volatile void __iomem *) addr);
}
static inline u8 inb(unsigned long addr)
{
return readb((volatile void __iomem *) addr);
}
static inline u16 inw(unsigned long addr)
{
return readw((volatile void __iomem *) addr);
}
static inline u32 inl(unsigned long addr)
{
return readl((volatile void __iomem *) addr);
}
static inline void outb(u8 b, unsigned long addr)
{
return writeb(b, (volatile void __iomem *) addr);
}
static inline void outw(u16 b, unsigned long addr)
{
return writew(b, (volatile void __iomem *) addr);
}
static inline void outl(u32 b, unsigned long addr)
{
return writel(b, (volatile void __iomem *) addr);
}
#define inb_p(addr) inb(addr)
#define inw_p(addr) inw(addr)
#define inl_p(addr) inl(addr)
#define outb_p(x, addr) outb((x), (addr))
#define outw_p(x, addr) outw((x), (addr))
#define outl_p(x, addr) outl((x), (addr))
static inline void insb(unsigned long addr, void *buffer, int count)
{
if (count) {
u8 *buf = buffer;
do {
u8 x = inb(addr);
*buf++ = x;
} while (--count);
}
}
static inline void insw(unsigned long addr, void *buffer, int count)
{
if (count) {
u16 *buf = buffer;
do {
u16 x = inw(addr);
*buf++ = x;
} while (--count);
}
}
static inline void insl(unsigned long addr, void *buffer, int count)
{
if (count) {
u32 *buf = buffer;
do {
u32 x = inl(addr);
*buf++ = x;
} while (--count);
}
}
static inline void outsb(unsigned long addr, const void *buffer, int count)
{
if (count) {
const u8 *buf = buffer;
do {
outb(*buf++, addr);
} while (--count);
}
}
static inline void outsw(unsigned long addr, const void *buffer, int count)
{
if (count) {
const u16 *buf = buffer;
do {
outw(*buf++, addr);
} while (--count);
}
}
extern void __outsl(unsigned long addr, const void *buffer, int count);
static inline void outsl(unsigned long addr, const void *buffer, int count)
{
if ((unsigned long) buffer & 0x3)
return __outsl(addr, buffer, count);
if (count) {
const u32 *buf = buffer;
do {
outl(*buf++, addr);
} while (--count);
}
}
#define ioread8(addr) readb(addr)
#define ioread16(addr) readw(addr)
#define ioread32(addr) readl(addr)
#define iowrite8(v, addr) writeb((v), (addr))
#define iowrite16(v, addr) writew((v), (addr))
#define iowrite32(v, addr) writel((v), (addr))
#define ioread16be(addr) be16_to_cpu(readw(addr))
#define ioread32be(addr) be32_to_cpu(readl(addr))
#define iowrite16be(v, addr) writew(cpu_to_be16(v), (addr))
#define iowrite32be(v, addr) writel(cpu_to_be32(v), (addr))
#define ioread8_rep(p, dst, count) \
insb((unsigned long) (p), (dst), (count))
#define ioread16_rep(p, dst, count) \
insw((unsigned long) (p), (dst), (count))
#define ioread32_rep(p, dst, count) \
insl((unsigned long) (p), (dst), (count))
#define iowrite8_rep(p, src, count) \
outsb((unsigned long) (p), (src), (count))
#define iowrite16_rep(p, src, count) \
outsw((unsigned long) (p), (src), (count))
#define iowrite32_rep(p, src, count) \
outsl((unsigned long) (p), (src), (count))
#define readsb(p, dst, count) \
insb((unsigned long) (p), (dst), (count))
#define readsw(p, dst, count) \
insw((unsigned long) (p), (dst), (count))
#define readsl(p, dst, count) \
insl((unsigned long) (p), (dst), (count))
#define writesb(p, src, count) \
outsb((unsigned long) (p), (src), (count))
#define writesw(p, src, count) \
outsw((unsigned long) (p), (src), (count))
#define writesl(p, src, count) \
outsl((unsigned long) (p), (src), (count))
#define IO_SPACE_LIMIT 0xffffffff
#ifdef __KERNEL__
#include <linux/vmalloc.h>
#define __io_virt(x) ((void *) (x))
/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
struct pci_dev;
static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p)
{
}
/*
* Change virtual addresses to physical addresses and vv.
* These are pretty trivial
*/
static inline unsigned long virt_to_phys(volatile void *address)
{
return __pa(address);
}
static inline void *phys_to_virt(unsigned long address)
{
return __va(address);
}
/*
* Change "struct page" to physical address.
*/
static inline void __iomem *__ioremap(unsigned long offset, unsigned long size,
unsigned long flags)
{
return (void __iomem *) offset;
}
static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
{
return (void __iomem *)(offset & ~0x20000000);
}
/*
* This one maps high address device memory and turns off caching for that
* area. it's useful if some control registers are in such an area and write
* combining or read caching is not desirable:
*/
static inline void __iomem *ioremap_nocache(unsigned long offset, unsigned long size)
{
return (void __iomem *) (offset | 0x20000000);
}
#define ioremap_wc ioremap_nocache
#define ioremap_wt ioremap_nocache
#define ioremap_uc ioremap_nocache
static inline void iounmap(void __iomem *addr)
{
}
static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
{
return (void __iomem *) port;
}
static inline void ioport_unmap(void __iomem *p)
{
}
#define xlate_dev_kmem_ptr(p) ((void *) (p))
#define xlate_dev_mem_ptr(p) ((void *) (p))
/*
* PCI bus iomem addresses must be in the region 0x80000000-0x9fffffff
*/
static inline unsigned long virt_to_bus(volatile void *address)
{
return ((unsigned long) address) & ~0x20000000;
}
static inline void *bus_to_virt(unsigned long address)
{
return (void *) address;
}
#define page_to_bus page_to_phys
#define memset_io(a, b, c) memset(__io_virt(a), (b), (c))
#define memcpy_fromio(a, b, c) memcpy((a), __io_virt(b), (c))
#define memcpy_toio(a, b, c) memcpy(__io_virt(a), (b), (c))
#endif /* __KERNEL__ */
#endif /* _ASM_IO_H */

40
arch/mn10300/include/asm/irq.h
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@ -1,40 +0,0 @@
/* MN10300 Hardware interrupt definitions
*
* Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Modified by David Howells (dhowells@redhat.com)
* - Derived from include/asm-i386/irq.h:
* - (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_IRQ_H
#define _ASM_IRQ_H
#include <asm/intctl-regs.h>
#include <asm/reset-regs.h>
#include <proc/irq.h>
/* this number is used when no interrupt has been assigned */
#define NO_IRQ INT_MAX
/*
* hardware irq numbers
* - the ASB2364 has an FPGA with an IRQ multiplexer on it
*/
#ifdef CONFIG_MN10300_UNIT_ASB2364
#include <unit/irq.h>
#else
#define NR_CPU_IRQS GxICR_NUM_IRQS
#define NR_IRQS NR_CPU_IRQS
#endif
/* external hardware irq numbers */
#define NR_XIRQS GxICR_NUM_XIRQS
#define irq_canonicalize(IRQ) (IRQ)
#endif /* _ASM_IRQ_H */

28
arch/mn10300/include/asm/irq_regs.h
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@ -1,28 +0,0 @@
/* MN10300 IRQ registers pointer definition
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_IRQ_REGS_H
#define _ASM_IRQ_REGS_H
/*
* Per-cpu current frame pointer - the location of the last exception frame on
* the stack
*/
#define ARCH_HAS_OWN_IRQ_REGS
#ifndef __ASSEMBLY__
static inline __attribute__((const))
struct pt_regs *get_irq_regs(void)
{
return current_frame();
}
#endif
#endif /* _ASM_IRQ_REGS_H */

215
arch/mn10300/include/asm/irqflags.h
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@ -1,215 +0,0 @@
/* MN10300 IRQ flag handling
*
* Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_IRQFLAGS_H
#define _ASM_IRQFLAGS_H
#include <asm/cpu-regs.h>
/* linux/smp.h <- linux/irqflags.h needs asm/smp.h first */
#include <asm/smp.h>
/*
* interrupt control
* - "disabled": run in IM1/2
* - level 0 - kernel debugger
* - level 1 - virtual serial DMA (if present)
* - level 5 - normal interrupt priority
* - level 6 - timer interrupt
* - "enabled": run in IM7
*/
#define MN10300_CLI_LEVEL (CONFIG_LINUX_CLI_LEVEL << EPSW_IM_SHIFT)
#ifndef __ASSEMBLY__
static inline unsigned long arch_local_save_flags(void)
{
unsigned long flags;
asm volatile("mov epsw,%0" : "=d"(flags));
return flags;
}
static inline void arch_local_irq_disable(void)
{
asm volatile(
" and %0,epsw \n"
" or %1,epsw \n"
" nop \n"
" nop \n"
" nop \n"
:
: "i"(~EPSW_IM), "i"(EPSW_IE | MN10300_CLI_LEVEL)
: "memory");
}
static inline unsigned long arch_local_irq_save(void)
{
unsigned long flags;
flags = arch_local_save_flags();
arch_local_irq_disable();
return flags;
}
/*
* we make sure arch_irq_enable() doesn't cause priority inversion
*/
extern unsigned long __mn10300_irq_enabled_epsw[];
static inline void arch_local_irq_enable(void)
{
unsigned long tmp;
int cpu = raw_smp_processor_id();
asm volatile(
" mov epsw,%0 \n"
" and %1,%0 \n"
" or %2,%0 \n"
" mov %0,epsw \n"
: "=&d"(tmp)
: "i"(~EPSW_IM), "r"(__mn10300_irq_enabled_epsw[cpu])
: "memory", "cc");
}
static inline void arch_local_irq_restore(unsigned long flags)
{
asm volatile(
" mov %0,epsw \n"
" nop \n"
" nop \n"
" nop \n"
:
: "d"(flags)
: "memory", "cc");
}
static inline bool arch_irqs_disabled_flags(unsigned long flags)
{
return (flags & (EPSW_IE | EPSW_IM)) != (EPSW_IE | EPSW_IM_7);
}
static inline bool arch_irqs_disabled(void)
{
return arch_irqs_disabled_flags(arch_local_save_flags());
}
/*
* Hook to save power by halting the CPU
* - called from the idle loop
* - must reenable interrupts (which takes three instruction cycles to complete)
*/
static inline void arch_safe_halt(void)
{
#ifdef CONFIG_SMP
arch_local_irq_enable();
#else
asm volatile(
" or %0,epsw \n"
" nop \n"
" nop \n"
" bset %2,(%1) \n"
:
: "i"(EPSW_IE|EPSW_IM), "n"(&CPUM), "i"(CPUM_SLEEP)
: "cc");
#endif
}
#define __sleep_cpu() \
do { \
asm volatile( \
" bset %1,(%0)\n" \
"1: btst %1,(%0)\n" \
" bne 1b\n" \
: \
: "i"(&CPUM), "i"(CPUM_SLEEP) \
: "cc" \
); \
} while (0)
static inline void arch_local_cli(void)
{
asm volatile(
" and %0,epsw \n"
" nop \n"
" nop \n"
" nop \n"
:
: "i"(~EPSW_IE)
: "memory"
);
}
static inline unsigned long arch_local_cli_save(void)
{
unsigned long flags = arch_local_save_flags();
arch_local_cli();
return flags;
}
static inline void arch_local_sti(void)
{
asm volatile(
" or %0,epsw \n"
:
: "i"(EPSW_IE)
: "memory");
}
static inline void arch_local_change_intr_mask_level(unsigned long level)
{
asm volatile(
" and %0,epsw \n"
" or %1,epsw \n"
:
: "i"(~EPSW_IM), "i"(EPSW_IE | level)
: "cc", "memory");
}
#else /* !__ASSEMBLY__ */
#define LOCAL_SAVE_FLAGS(reg) \
mov epsw,reg
#define LOCAL_IRQ_DISABLE \
and ~EPSW_IM,epsw; \
or EPSW_IE|MN10300_CLI_LEVEL,epsw; \
nop; \
nop; \
nop
#define LOCAL_IRQ_ENABLE \
or EPSW_IE|EPSW_IM_7,epsw
#define LOCAL_IRQ_RESTORE(reg) \
mov reg,epsw
#define LOCAL_CLI_SAVE(reg) \
mov epsw,reg; \
and ~EPSW_IE,epsw; \
nop; \
nop; \
nop
#define LOCAL_CLI \
and ~EPSW_IE,epsw; \
nop; \
nop; \
nop
#define LOCAL_STI \
or EPSW_IE,epsw
#define LOCAL_CHANGE_INTR_MASK_LEVEL(level) \
and ~EPSW_IM,epsw; \
or EPSW_IE|(level),epsw
#endif /* __ASSEMBLY__ */
#endif /* _ASM_IRQFLAGS_H */

22
arch/mn10300/include/asm/kdebug.h
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@ -1,22 +0,0 @@
/* MN10300 In-kernel death knells
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_KDEBUG_H
#define _ASM_KDEBUG_H
/* Grossly misnamed. */
enum die_val {
DIE_OOPS = 1,
DIE_BREAKPOINT,
DIE_GPF,
};
#endif /* _ASM_KDEBUG_H */

81
arch/mn10300/include/asm/kgdb.h
View file

@ -1,81 +0,0 @@
/* Kernel debugger for MN10300
*
* Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public Licence
* as published by the Free Software Foundation; either version
* 2 of the Licence, or (at your option) any later version.
*/
#ifndef _ASM_KGDB_H
#define _ASM_KGDB_H
/*
* BUFMAX defines the maximum number of characters in inbound/outbound
* buffers at least NUMREGBYTES*2 are needed for register packets
* Longer buffer is needed to list all threads
*/
#define BUFMAX 1024
/*
* Note that this register image is in a different order than the register
* image that Linux produces at interrupt time.
*/
enum regnames {
GDB_FR_D0 = 0,
GDB_FR_D1 = 1,
GDB_FR_D2 = 2,
GDB_FR_D3 = 3,
GDB_FR_A0 = 4,
GDB_FR_A1 = 5,
GDB_FR_A2 = 6,
GDB_FR_A3 = 7,
GDB_FR_SP = 8,
GDB_FR_PC = 9,
GDB_FR_MDR = 10,
GDB_FR_EPSW = 11,
GDB_FR_LIR = 12,
GDB_FR_LAR = 13,
GDB_FR_MDRQ = 14,
GDB_FR_E0 = 15,
GDB_FR_E1 = 16,
GDB_FR_E2 = 17,
GDB_FR_E3 = 18,
GDB_FR_E4 = 19,
GDB_FR_E5 = 20,
GDB_FR_E6 = 21,
GDB_FR_E7 = 22,
GDB_FR_SSP = 23,
GDB_FR_MSP = 24,
GDB_FR_USP = 25,
GDB_FR_MCRH = 26,
GDB_FR_MCRL = 27,
GDB_FR_MCVF = 28,
GDB_FR_FPCR = 29,
GDB_FR_DUMMY0 = 30,
GDB_FR_DUMMY1 = 31,
GDB_FR_FS0 = 32,
GDB_FR_SIZE = 64,
};
#define GDB_ORIG_D0 41
#define NUMREGBYTES (GDB_FR_SIZE*4)
static inline void arch_kgdb_breakpoint(void)
{
asm(".globl __arch_kgdb_breakpoint; __arch_kgdb_breakpoint: break");
}
extern u8 __arch_kgdb_breakpoint;
#define BREAK_INSTR_SIZE 1
#define CACHE_FLUSH_IS_SAFE 1
#endif /* _ASM_KGDB_H */

7
arch/mn10300/include/asm/kmap_types.h
View file

@ -1,7 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_KMAP_TYPES_H
#define _ASM_KMAP_TYPES_H
#include <asm-generic/kmap_types.h>
#endif /* _ASM_KMAP_TYPES_H */

55
arch/mn10300/include/asm/kprobes.h
View file

@ -1,55 +0,0 @@
/* MN10300 Kernel Probes support
*
* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
* Written by Mark Salter (msalter@redhat.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public Licence as published by
* the Free Software Foundation; either version 2 of the Licence, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public Licence for more details.
*
* You should have received a copy of the GNU General Public Licence
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
*/
#ifndef _ASM_KPROBES_H
#define _ASM_KPROBES_H
#include <asm-generic/kprobes.h>
#define BREAKPOINT_INSTRUCTION 0xff
#ifdef CONFIG_KPROBES
#include <linux/types.h>
#include <linux/ptrace.h>
struct kprobe;
typedef unsigned char kprobe_opcode_t;
#define MAX_INSN_SIZE 8
#define MAX_STACK_SIZE 128
/* Architecture specific copy of original instruction */
struct arch_specific_insn {
/* copy of original instruction
*/
kprobe_opcode_t insn[MAX_INSN_SIZE];
};
extern const int kretprobe_blacklist_size;
extern int kprobe_exceptions_notify(struct notifier_block *self,
unsigned long val, void *data);
#define flush_insn_slot(p) do {} while (0)
extern void arch_remove_kprobe(struct kprobe *p);
#endif /* CONFIG_KPROBES */
#endif /* _ASM_KPROBES_H */

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