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spi: Updates for v6.16

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A small set of updates that came in during the merge window, we've got:
 
  - Some small fixes for the Broadcom and spi-pci1xxxx drivers
  - A change to the QPIC SNAND driver to flag that the error correction
    features are less useful than people might be expecting.
  - A new device ID for the SOPHGO SG2042.
  - The addition of Yang Shen as a Huawei maintainer.
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Merge tag 'spi-v6.16-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull more spi updates from Mark Brown:
 "A small set of updates that came in during the merge window, we've
  got:

   - Some small fixes for the Broadcom and spi-pci1xxxx drivers

   - A change to the QPIC SNAND driver to flag that the error correction
     features are less useful than people might be expecting

   - A new device ID for the SOPHGO SG2042

   - The addition of Yang Shen as a Huawei maintainer"

* tag 'spi-v6.16-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
  spi: spi-qpic-snand: document the limited bit error reporting capability
  spi: bcm63xx-hsspi: fix shared reset
  spi: bcm63xx-spi: fix shared reset
  MAINTAINERS: Update HiSilicon SFC driver maintainer
  MAINTAINERS: Update HiSilicon SPI Controller driver maintainer
  spi: dt-bindings: spi-sg2044-nor: Add SOPHGO SG2042
  spi: spi-pci1xxxx: Fix Probe failure with Dual SPI instance with INTx interrupts
This commit is contained in:
Linus Torvalds 2025-06-06 13:22:31 -07:00
commit 7a912d0441
6 changed files with 58 additions and 19 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

7
Documentation/devicetree/bindings/spi/spi-sg2044-nor.yaml
View file

@ -14,7 +14,12 @@ allOf:
properties:
compatible:
const: sophgo,sg2044-spifmc-nor
oneOf:
- const: sophgo,sg2044-spifmc-nor
- items:
- enum:
- sophgo,sg2042-spifmc-nor
- const: sophgo,sg2044-spifmc-nor
reg:
maxItems: 1

4
MAINTAINERS
View file

@ -10966,7 +10966,7 @@ F: drivers/crypto/hisilicon/sec2/sec_crypto.h
F: drivers/crypto/hisilicon/sec2/sec_main.c
HISILICON SPI Controller DRIVER FOR KUNPENG SOCS
M: Jay Fang <f.fangjian@huawei.com>
M: Yang Shen <shenyang39@huawei.com>
L: linux-spi@vger.kernel.org
S: Maintained
W: http://www.hisilicon.com
@ -10992,7 +10992,7 @@ S: Maintained
F: drivers/crypto/hisilicon/trng/trng.c
HISILICON V3XX SPI NOR FLASH Controller Driver
M: Jay Fang <f.fangjian@huawei.com>
M: Yang Shen <shenyang39@huawei.com>
S: Maintained
W: http://www.hisilicon.com
F: drivers/spi/spi-hisi-sfc-v3xx.c

2
drivers/spi/spi-bcm63xx-hsspi.c
View file

@ -745,7 +745,7 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev)
if (IS_ERR(clk))
return PTR_ERR(clk);
reset = devm_reset_control_get_optional_exclusive(dev, NULL);
reset = devm_reset_control_get_optional_shared(dev, NULL);
if (IS_ERR(reset))
return PTR_ERR(reset);

2
drivers/spi/spi-bcm63xx.c
View file

@ -523,7 +523,7 @@ static int bcm63xx_spi_probe(struct platform_device *pdev)
return PTR_ERR(clk);
}
reset = devm_reset_control_get_optional_exclusive(dev, NULL);
reset = devm_reset_control_get_optional_shared(dev, NULL);
if (IS_ERR(reset))
return PTR_ERR(reset);

24
drivers/spi/spi-pci1xxxx.c
View file

@ -685,6 +685,17 @@ static irqreturn_t pci1xxxx_spi_isr(int irq, void *dev)
return pci1xxxx_spi_isr_io(irq, dev);
}
static irqreturn_t pci1xxxx_spi_shared_isr(int irq, void *dev)
{
struct pci1xxxx_spi *par = dev;
u8 i = 0;
for (i = 0; i < par->total_hw_instances; i++)
pci1xxxx_spi_isr(irq, par->spi_int[i]);
return IRQ_HANDLED;
}
static bool pci1xxxx_spi_can_dma(struct spi_controller *host,
struct spi_device *spi,
struct spi_transfer *xfer)
@ -702,6 +713,7 @@ static int pci1xxxx_spi_probe(struct pci_dev *pdev, const struct pci_device_id *
struct device *dev = &pdev->dev;
struct pci1xxxx_spi *spi_bus;
struct spi_controller *spi_host;
int num_vector = 0;
u32 regval;
int ret;
@ -749,9 +761,9 @@ static int pci1xxxx_spi_probe(struct pci_dev *pdev, const struct pci_device_id *
if (!spi_bus->reg_base)
return -EINVAL;
ret = pci_alloc_irq_vectors(pdev, hw_inst_cnt, hw_inst_cnt,
num_vector = pci_alloc_irq_vectors(pdev, 1, hw_inst_cnt,
PCI_IRQ_ALL_TYPES);
if (ret < 0) {
if (num_vector < 0) {
dev_err(&pdev->dev, "Error allocating MSI vectors\n");
return ret;
}
@ -765,9 +777,15 @@ static int pci1xxxx_spi_probe(struct pci_dev *pdev, const struct pci_device_id *
SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst));
spi_sub_ptr->irq = pci_irq_vector(pdev, 0);
if (num_vector >= hw_inst_cnt)
ret = devm_request_irq(&pdev->dev, spi_sub_ptr->irq,
pci1xxxx_spi_isr, PCI1XXXX_IRQ_FLAGS,
pci_name(pdev), spi_sub_ptr);
else
ret = devm_request_irq(&pdev->dev, spi_sub_ptr->irq,
pci1xxxx_spi_shared_isr,
PCI1XXXX_IRQ_FLAGS | IRQF_SHARED,
pci_name(pdev), spi_bus);
if (ret < 0) {
dev_err(&pdev->dev, "Unable to request irq : %d",
spi_sub_ptr->irq);
@ -798,6 +816,7 @@ static int pci1xxxx_spi_probe(struct pci_dev *pdev, const struct pci_device_id *
regval &= ~SPI_INTR;
writel(regval, spi_bus->reg_base +
SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst));
if (num_vector >= hw_inst_cnt) {
spi_sub_ptr->irq = pci_irq_vector(pdev, iter);
ret = devm_request_irq(&pdev->dev, spi_sub_ptr->irq,
pci1xxxx_spi_isr, PCI1XXXX_IRQ_FLAGS,
@ -808,6 +827,7 @@ static int pci1xxxx_spi_probe(struct pci_dev *pdev, const struct pci_device_id *
return -ENODEV;
}
}
}
spi_host = spi_sub_ptr->spi_host;
spi_host->num_chipselect = SPI_CHIP_SEL_COUNT;

14
drivers/spi/spi-qpic-snand.c
View file

@ -639,6 +639,20 @@ static int qcom_spi_check_error(struct qcom_nand_controller *snandc)
unsigned int stat;
stat = buffer & BS_CORRECTABLE_ERR_MSK;
/*
* The exact number of the corrected bits is
* unknown because the hardware only reports the
* number of the corrected bytes.
*
* Since we have no better solution at the moment,
* report that value as the number of bit errors
* despite that it is inaccurate in most cases.
*/
if (stat && stat != ecc_cfg->strength)
dev_warn_once(snandc->dev,
"Warning: due to hw limitation, the reported number of the corrected bits may be inaccurate\n");
snandc->qspi->ecc_stats.corrected += stat;
max_bitflips = max(max_bitflips, stat);
}